forked from OSchip/llvm-project
parent
0c14000760
commit
0e0b599d29
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@ -64,10 +64,6 @@ namespace {
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
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setOperationAction(ISD::SREM , MVT::f64 , Expand);
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setOperationAction(ISD::SREM , MVT::f64 , Expand);
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// We don't support these yet.
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setOperationAction(ISD::FNEG , MVT::f64 , Expand);
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setOperationAction(ISD::FABS , MVT::f64 , Expand);
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// These should be promoted to a larger select which is supported.
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// These should be promoted to a larger select which is supported.
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/**/ setOperationAction(ISD::SELECT , MVT::i1 , Promote);
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/**/ setOperationAction(ISD::SELECT , MVT::i1 , Promote);
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setOperationAction(ISD::SELECT , MVT::i8 , Promote);
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setOperationAction(ISD::SELECT , MVT::i8 , Promote);
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@ -1812,6 +1808,16 @@ unsigned ISel::SelectExpr(SDOperand N) {
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
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return Result;
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return Result;
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case ISD::FABS:
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Tmp1 = SelectExpr(Node->getOperand(0));
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BuildMI(BB, X86::FABS, 1, Result).addReg(Tmp1);
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return Result;
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case ISD::FNEG:
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Tmp1 = SelectExpr(Node->getOperand(0));
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BuildMI(BB, X86::FCHS, 1, Result).addReg(Tmp1);
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return Result;
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case ISD::SUB:
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case ISD::SUB:
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case ISD::MUL:
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case ISD::MUL:
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case ISD::AND:
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case ISD::AND:
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