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GlobalISel: fix SUBREG_TO_REG implementation. 

The first argument needs to be an immediate rather than a register. Should fix
some crashes in the verifier bot.

llvm-svn: 308540
This commit is contained in:
Tim Northover 2017-07-19 22:08:08 +00:00
parent 57e15cd40a
commit 0e0b3c97dd
2 changed files with 26 additions and 3 deletions
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25
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
View File

@ -780,6 +780,29 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
case TargetOpcode::G_UNMERGE_VALUES: {
//
LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
// Larger extracts are vectors, same-size extracts should be something else
// by now (either split up or simplified to a COPY).
if (SrcTy.getSizeInBits() > 64 || Ty.getSizeInBits() > 32)
return false;
I.setDesc(TII.get(AArch64::UBFMXri));
MachineInstrBuilder(MF, I).addImm(I.getOperand(2).getImm() +
Ty.getSizeInBits() - 1);
unsigned DstReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
BuildMI(MBB, std::next(I.getIterator()), I.getDebugLoc(),
TII.get(AArch64::COPY))
.addDef(I.getOperand(0).getReg())
.addUse(DstReg, 0, AArch64::sub_32);
RBI.constrainGenericRegister(I.getOperand(0).getReg(),
AArch64::GPR32RegClass, MRI);
I.getOperand(0).setReg(DstReg);
return constrainSelectedInstRegOperands(I, TII, TRI, RBI);
}
case TargetOpcode::G_INSERT: {
LLT SrcTy = MRI.getType(I.getOperand(2).getReg());
@ -798,7 +821,7 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const {
BuildMI(MBB, I.getIterator(), I.getDebugLoc(),
TII.get(AArch64::SUBREG_TO_REG))
.addDef(SrcReg)
.addUse(0)
.addImm(0)
.addUse(I.getOperand(2).getReg())
.addImm(AArch64::sub_32);
RBI.constrainGenericRegister(I.getOperand(2).getReg(),

4
llvm/test/CodeGen/AArch64/GlobalISel/select-insert-extract.mir
View File

@ -15,11 +15,11 @@ body: |
%1:gpr(s64) = G_IMPLICIT_DEF
; CHECK: body:
; CHECK: [[TMP:%[0-9]+]] = SUBREG_TO_REG _, %0, 15
; CHECK: [[TMP:%[0-9]+]] = SUBREG_TO_REG 0, %0, 15
; CHECK: %2 = BFMXri %1, [[TMP]], 0, 31
%2:gpr(s64) = G_INSERT %1, %0, 0
; CHECK: [[TMP:%[0-9]+]] = SUBREG_TO_REG _, %0, 15
; CHECK: [[TMP:%[0-9]+]] = SUBREG_TO_REG 0, %0, 15
; CHECK: %3 = BFMXri %1, [[TMP]], 51, 31
%3:gpr(s64) = G_INSERT %1, %0, 13