forked from OSchip/llvm-project
ARM: Do not add reserved registers to block livein lists; NFC
llvm-svn: 304266
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4e9736b1c9
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@ -968,8 +968,9 @@ void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB,
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if (Reg >= ARM::D8 && Reg < ARM::D8 + NumAlignedDPRCS2Regs)
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continue;
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bool isLiveIn = MF.getRegInfo().isLiveIn(Reg);
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if (!isLiveIn)
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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bool isLiveIn = MRI.isLiveIn(Reg);
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if (!isLiveIn && !MRI.isReserved(Reg))
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MBB.addLiveIn(Reg);
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// If NoGap is true, push consecutive registers and then leave the rest
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// for other instructions. e.g.
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@ -698,13 +698,14 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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CopyRegs.insert(ArgReg);
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// Push the low registers and lr
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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if (!LoRegsToSave.empty()) {
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MachineInstrBuilder MIB =
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BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)).add(predOps(ARMCC::AL));
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for (unsigned Reg : {ARM::R4, ARM::R5, ARM::R6, ARM::R7, ARM::LR}) {
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if (LoRegsToSave.count(Reg)) {
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bool isKill = !MF.getRegInfo().isLiveIn(Reg);
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if (isKill)
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bool isKill = !MRI.isLiveIn(Reg);
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if (isKill && !MRI.isReserved(Reg))
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MBB.addLiveIn(Reg);
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MIB.addReg(Reg, getKillRegState(isKill));
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@ -746,8 +747,8 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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SmallVector<unsigned, 4> RegsToPush;
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while (HiRegToSave != AllHighRegsEnd && CopyReg != AllCopyRegsEnd) {
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if (HiRegsToSave.count(*HiRegToSave)) {
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bool isKill = !MF.getRegInfo().isLiveIn(*HiRegToSave);
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if (isKill)
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bool isKill = !MRI.isLiveIn(*HiRegToSave);
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if (isKill && !MRI.isReserved(*HiRegToSave))
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MBB.addLiveIn(*HiRegToSave);
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// Emit a MOV from the high reg to the low reg.
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