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[mips] In performDSPShiftCombine, check that all elements in the vector are 

shifted by the same amount and the shift amount is smaller than the element
size.

llvm-svn: 180039
This commit is contained in:
Akira Hatanaka 2013-04-22 19:58:23 +00:00
parent 09a3912b5c
commit 0d6964cf4a
3 changed files with 68 additions and 10 deletions
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14
llvm/lib/Target/Mips/MipsDSPInstrInfo.td
View File

@ -1288,18 +1288,18 @@ def : DSPBinPat<ADDWC, i32, adde>;
// Shift immediate patterns.
class DSPShiftPat<Instruction Inst, ValueType ValTy, SDPatternOperator Node,
ImmLeaf Imm, Predicate Pred = HasDSP> :
SDPatternOperator Imm, Predicate Pred = HasDSP> :
DSPPat<(Node ValTy:$a, Imm:$shamt), (Inst ValTy:$a, Imm:$shamt), Pred>;
def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, immZExt4>;
def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, immZExt4>;
def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, immZExt4, HasDSPR2>;
def : DSPShiftPat<SHLL_PH, v2i16, MipsSHLL_DSP, imm>;
def : DSPShiftPat<SHRA_PH, v2i16, MipsSHRA_DSP, imm>;
def : DSPShiftPat<SHRL_PH, v2i16, MipsSHRL_DSP, imm, HasDSPR2>;
def : DSPShiftPat<SHLL_PH, v2i16, int_mips_shll_ph, immZExt4>;
def : DSPShiftPat<SHRA_PH, v2i16, int_mips_shra_ph, immZExt4>;
def : DSPShiftPat<SHRL_PH, v2i16, int_mips_shrl_ph, immZExt4, HasDSPR2>;
def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, immZExt3>;
def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, immZExt3, HasDSPR2>;
def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, immZExt3>;
def : DSPShiftPat<SHLL_QB, v4i8, MipsSHLL_DSP, imm>;
def : DSPShiftPat<SHRA_QB, v4i8, MipsSHRA_DSP, imm, HasDSPR2>;
def : DSPShiftPat<SHRL_QB, v4i8, MipsSHRL_DSP, imm>;
def : DSPShiftPat<SHLL_QB, v4i8, int_mips_shll_qb, immZExt3>;
def : DSPShiftPat<SHRA_QB, v4i8, int_mips_shra_qb, immZExt3, HasDSPR2>;
def : DSPShiftPat<SHRL_QB, v4i8, int_mips_shrl_qb, immZExt3>;

8
llvm/lib/Target/Mips/MipsSEISelLowering.cpp
View File

@ -327,9 +327,11 @@ static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
if (!BV || !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
HasAnyUndefs, EltSize,
!Subtarget->isLittle()))
if (!BV ||
!BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, EltSize,
!Subtarget->isLittle()) ||
(SplatBitSize != EltSize) ||
!isUIntN(Log2_32(EltSize), SplatValue.getZExtValue()))
return SDValue();
return DAG.getNode(Opc, N->getDebugLoc(), Ty, N->getOperand(0),

56
llvm/test/CodeGen/Mips/dsp-patterns.ll
View File

@ -203,3 +203,59 @@ entry:
%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
ret { i32 } %.fca.0.insert
}
; Check that shift node is expanded if splat element size is not 16-bit.
;
; R1: test_vector_splat_imm_v2q15:
; R1-NOT: shll.ph
define { i32 } @test_vector_splat_imm_v2q15(i32 %a.coerce) {
entry:
%0 = bitcast i32 %a.coerce to <2 x i16>
%shl = shl <2 x i16> %0, <i16 0, i16 2>
%1 = bitcast <2 x i16> %shl to i32
%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
ret { i32 } %.fca.0.insert
}
; Check that shift node is expanded if splat element size is not 8-bit.
;
; R1: test_vector_splat_imm_v4i8:
; R1-NOT: shll.qb
define { i32 } @test_vector_splat_imm_v4i8(i32 %a.coerce) {
entry:
%0 = bitcast i32 %a.coerce to <4 x i8>
%shl = shl <4 x i8> %0, <i8 0, i8 2, i8 0, i8 2>
%1 = bitcast <4 x i8> %shl to i32
%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
ret { i32 } %.fca.0.insert
}
; Check that shift node is expanded if shift amount doesn't fit in 4-bit sa field.
;
; R1: test_shift_amount_v2q15:
; R1-NOT: shll.ph
define { i32 } @test_shift_amount_v2q15(i32 %a.coerce) {
entry:
%0 = bitcast i32 %a.coerce to <2 x i16>
%shl = shl <2 x i16> %0, <i16 16, i16 16>
%1 = bitcast <2 x i16> %shl to i32
%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
ret { i32 } %.fca.0.insert
}
; Check that shift node is expanded if shift amount doesn't fit in 3-bit sa field.
;
; R1: test_shift_amount_v4i8:
; R1-NOT: shll.qb
define { i32 } @test_shift_amount_v4i8(i32 %a.coerce) {
entry:
%0 = bitcast i32 %a.coerce to <4 x i8>
%shl = shl <4 x i8> %0, <i8 8, i8 8, i8 8, i8 8>
%1 = bitcast <4 x i8> %shl to i32
%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
ret { i32 } %.fca.0.insert
}