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Add support for the LLVM FNeg instruction 

Closes tensorflow/mlir#216

COPYBARA_INTEGRATE_REVIEW=https://github.com/tensorflow/mlir/pull/216 from schweitzpgi:llvmir-fneg-op f9b5f185845d671b745ab6fc213d5d9aff044b34
PiperOrigin-RevId: 278795325
This commit is contained in:
Eric Schweitz 2019-11-05 23:39:25 -08:00 committed by A. Unique TensorFlower
parent 146f7de50d
commit 0d545921ea
3 changed files with 16 additions and 0 deletions
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10
mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
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@ -132,6 +132,15 @@ class LLVM_ArithmeticOp<string mnemonic, string builderFunc,
let parser = [{ return impl::parseOneResultSameOperandTypeOp(parser, result); }];
let printer = [{ mlir::impl::printOneResultOp(this->getOperation(), p); }];
}
class LLVM_UnaryArithmeticOp<string mnemonic, string builderFunc,
list<OpTrait> traits = []> :
LLVM_OneResultOp<mnemonic,
!listconcat([NoSideEffect, SameOperandsAndResultType], traits)>,
Arguments<(ins LLVM_Type:$operand)>,
LLVM_Builder<"$res = builder." # builderFunc # "($operand);"> {
let parser = [{ return impl::parseOneResultSameOperandTypeOp(parser, result); }];
let printer = [{ mlir::impl::printOneResultOp(this->getOperation(), p); }];
}
// Integer binary operations.
def LLVM_AddOp : LLVM_ArithmeticOp<"add", "CreateAdd", [Commutative]>;
@ -247,6 +256,7 @@ def LLVM_FSubOp : LLVM_ArithmeticOp<"fsub", "CreateFSub">;
def LLVM_FMulOp : LLVM_ArithmeticOp<"fmul", "CreateFMul">;
def LLVM_FDivOp : LLVM_ArithmeticOp<"fdiv", "CreateFDiv">;
def LLVM_FRemOp : LLVM_ArithmeticOp<"frem", "CreateFRem">;
def LLVM_FNegOp : LLVM_UnaryArithmeticOp<"fneg", "CreateFNeg">;
// Memory-related operations.
def LLVM_AllocaOp :

3
mlir/test/Dialect/LLVMIR/roundtrip.mlir
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@ -94,6 +94,9 @@ func @ops(%arg0 : !llvm.i32, %arg1 : !llvm.float) {
%27 = llvm.fpext %arg1 : !llvm.float to !llvm.x86_fp80
%28 = llvm.fpext %arg1 : !llvm.float to !llvm.fp128
// CHECK: %29 = llvm.fneg %arg1 : !llvm.float
%29 = llvm.fneg %arg1 : !llvm.float
// CHECK: llvm.return
llvm.return
}

3
mlir/test/Target/llvmir.mlir
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@ -811,6 +811,9 @@ llvm.func @ops(%arg0: !llvm.float, %arg1: !llvm.float, %arg2: !llvm.i32, %arg3:
// CHECK-NEXT: %22 = ashr i32 %2, %3
%18 = llvm.ashr %arg2, %arg3 : !llvm.i32
// CHECK-NEXT: fneg float %0
%19 = llvm.fneg %arg0 : !llvm.float
llvm.return %10 : !llvm<"{ float, i32 }">
}