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[x86] update checks 

llvm-svn: 275064
This commit is contained in:
Sanjay Patel 2016-07-11 14:07:31 +00:00
parent a452db4d0f
commit 0d38830aca
1 changed files with 30 additions and 15 deletions
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45
llvm/test/CodeGen/X86/shift-pcmp.ll
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@ -1,18 +1,20 @@
; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse2 | FileCheck %s
; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+avx | FileCheck %s
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+sse2 | FileCheck %s --check-prefix=SSE
; RUN: llc < %s -o - -mcpu=generic -march=x86-64 -mattr=+avx | FileCheck %s --check-prefix=AVX
define <8 x i16> @foo(<8 x i16> %a, <8 x i16> %b) {
; CHECK: .short 32
; CHECK-NEXT: .short 32
; CHECK-NEXT: .short 32
; CHECK-NEXT: .short 32
; CHECK-NEXT: .short 32
; CHECK-NEXT: .short 32
; CHECK-NEXT: .short 32
; CHECK-NEXT: .short 32
; CHECK-LABEL: {{^_?foo:}}
; CHECK-NOT: psll
entry:
; SSE-LABEL: foo:
; SSE: ## BB#0:
; SSE-NEXT: pcmpeqw %xmm1, %xmm0
; SSE-NEXT: pand {{.*}}(%rip), %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: foo:
; AVX: ## BB#0:
; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: retq
;
%icmp = icmp eq <8 x i16> %a, %b
%zext = zext <8 x i1> %icmp to <8 x i16>
%shl = shl nuw nsw <8 x i16> %zext, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
@ -21,10 +23,23 @@ entry:
; Don't fail with an assert due to an undef in the buildvector
define <8 x i16> @bar(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: bar
entry:
; SSE-LABEL: bar:
; SSE: ## BB#0:
; SSE-NEXT: pcmpeqw %xmm1, %xmm0
; SSE-NEXT: pand {{.*}}(%rip), %xmm0
; SSE-NEXT: psllw $5, %xmm0
; SSE-NEXT: retq
;
; AVX-LABEL: bar:
; AVX: ## BB#0:
; AVX-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpsllw $5, %xmm0, %xmm0
; AVX-NEXT: retq
;
%icmp = icmp eq <8 x i16> %a, %b
%zext = zext <8 x i1> %icmp to <8 x i16>
%shl = shl nuw nsw <8 x i16> %zext, <i16 5, i16 undef, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>
ret <8 x i16> %shl
}