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[mips][micromips] Fix (dis)assembly of bc1(t|f) 

Previously these instructions were marked codegen only and had
an under-specified instruction description that did not record the
fcc register.

Reviewers: atanasyan, abeserminji

Differential Revision: https://reviews.llvm.org/D38847

llvm-svn: 315905
This commit is contained in:
Simon Dardis 2017-10-16 14:20:22 +00:00
parent 7508fbd581
commit 0d378a9eed
6 changed files with 32 additions and 17 deletions
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14
llvm/lib/Target/Mips/MicroMipsInstrFPU.td
View File

@ -58,10 +58,16 @@ def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>,
bits<3> fcc = 0;
}
def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
BC1F_FM_MM<0x1c>, ISA_MICROMIPS32_NOT_MIPS32R6;
def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
BC1F_FM_MM<0x1d>, ISA_MICROMIPS32_NOT_MIPS32R6;
}
let DecoderNamespace = "MicroMips" in {
def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>,
BC1F_FM_MM<0x1c>, ISA_MICROMIPS32_NOT_MIPS32R6;
def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>,
BC1F_FM_MM<0x1d>, ISA_MICROMIPS32_NOT_MIPS32R6;
}
let isCodeGenOnly = 1 in {
def CVT_W_S_MM : MMRel, ABSS_FT<"cvt.w.s", FGR32Opnd, FGR32Opnd, II_CVT>,
ROUND_W_FM_MM<0, 0x24>, ISA_MICROMIPS;
def ROUND_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"round.w.s", FGR32Opnd, FGR32Opnd,

3
llvm/lib/Target/Mips/MicroMipsInstrFormats.td
View File

@ -786,13 +786,14 @@ class C_COND_FM_MM<bits <2> fmt, bits<4> c> : CEQS_FM_MM<fmt> {
}
class BC1F_FM_MM<bits<5> tf> : MMArch {
bits<3> fcc;
bits<16> offset;
bits<32> Inst;
let Inst{31-26} = 0x10;
let Inst{25-21} = tf;
let Inst{20-18} = 0x0; // cc
let Inst{20-18} = fcc; // cc
let Inst{17-16} = 0x0;
let Inst{15-0} = offset;
}

18
llvm/lib/Target/Mips/MipsInstrFPU.td
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@ -641,17 +641,17 @@ let AdditionalPredicates = [NoNaNsFPMath, HasMadd4],
def MIPS_BRANCH_F : PatLeaf<(i32 0)>;
def MIPS_BRANCH_T : PatLeaf<(i32 1)>;
def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,
BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,
BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
let AdditionalPredicates = [NotInMicroMips] in {
def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
BC1F_FM<0, 0>, ISA_MIPS1_NOT_32R6_64R6;
def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,
BC1F_FM<1, 0>, ISA_MIPS2_NOT_32R6_64R6;
def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
BC1F_FM<0, 1>, ISA_MIPS1_NOT_32R6_64R6;
def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,
BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6;
/// Floating Point Compare
let AdditionalPredicates = [NotInMicroMips] in {
def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>,
ISA_MIPS1_NOT_32R6_64R6 {

2
llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
View File

@ -55,6 +55,8 @@
0x26 0x11 0x67 0x45 # CHECK: addi $9, $6, 17767
0x26 0x31 0x67 0xc5 # CHECK: addiu $9, $6, -15001
0xe6 0x00 0x50 0x49 # CHECK: addu $9, $6, $7
0x80 0x43 0xe6 0xff # CHECK: bc1f -48
0xa0 0x43 0xe2 0xff # CHECK: bc1t -56
0xe6 0x00 0x90 0x49 # CHECK: sub $9, $6, $7
0xa3 0x00 0xd0 0x21 # CHECK: subu $4, $3, $5
0xe0 0x00 0x90 0x31 # CHECK: sub $6, $zero, $7

2
llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt
View File

@ -55,6 +55,8 @@
0x11 0x26 0x45 0x67 # CHECK: addi $9, $6, 17767
0x31 0x26 0xc5 0x67 # CHECK: addiu $9, $6, -15001
0x00 0xe6 0x49 0x50 # CHECK: addu $9, $6, $7
0x43 0x80 0xff 0xe6 # CHECK: bc1f -48
0x43 0xa0 0xff 0xe2 # CHECK: bc1t -56
0x00 0xe6 0x49 0x90 # CHECK: sub $9, $6, $7
0x00 0xa3 0x21 0xd0 # CHECK: subu $4, $3, $5
0x00 0xe0 0x31 0x90 # CHECK: sub $6, $zero, $7

10
llvm/test/MC/Mips/micromips/valid.s
View File

@ -1,4 +1,4 @@
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mattr=micromips | FileCheck %s
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mattr=micromips | FileCheck %s
.set noat
addiusp -16 # CHECK: addiusp -16 # encoding: [0x4f,0xf9]
@ -243,9 +243,13 @@ c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x5
c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x57,0x16,0xc4,0x7c]
c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x54,0x9e,0x20,0x7c]
bc1t 8 # CHECK: bc1t 8 # encoding: [0x43,0xa0,0x00,0x04]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1T_MM
bc1f 16 # CHECK: bc1f 16 # encoding: [0x43,0x80,0x00,0x08]
bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x43,0xa0,0x00,0x02]
bc1f $fcc2, -20 # CHECK: bc1f $fcc2, -20 # encoding: [0x43,0x80,0xff,0xf6]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1F_MM
bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x43,0xa4,0x00,0x02]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1T_MM
bc1f $fcc2, -20 # CHECK: bc1f $fcc2, -20 # encoding: [0x43,0x88,0xff,0xf6]
# CHECK-NEXT: # <MCInst #{{[0-9]+}} BC1F_MM
sync # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c]
sync 0 # CHECK: sync 0 # encoding: [0x00,0x00,0x6b,0x7c]
sync 1 # CHECK: sync 1 # encoding: [0x00,0x01,0x6b,0x7c]