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AVX-512: fixed asm string of vsqrtss 

(vvsqrtss was generated before)

llvm-svn: 254411
This commit is contained in:
Elena Demikhovsky 2015-12-01 12:43:46 +00:00
parent aa1f17ea95
commit 0d0692d854
1 changed files with 2 additions and 2 deletions
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4
llvm/lib/Target/X86/X86InstrAVX512.td
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@ -5911,12 +5911,12 @@ multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,X86VectorVTInfo _,
EVEX_B, EVEX_RC; EVEX_B, EVEX_RC;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def r : SI<opc, MRMSrcReg, (outs _.FRC:$dst), def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
(ins _.FRC:$src1, _.FRC:$src2), (ins _.FRC:$src1, _.FRC:$src2),
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>; OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
let mayLoad = 1 in let mayLoad = 1 in
def m : SI<opc, MRMSrcMem, (outs _.FRC:$dst), def m : I<opc, MRMSrcMem, (outs _.FRC:$dst),
(ins _.FRC:$src1, _.ScalarMemOp:$src2), (ins _.FRC:$src1, _.ScalarMemOp:$src2),
OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>; OpcodeStr#"\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>;
} }