From 0cdbc7a2ca4cc45817790790be15d78e2bf27310 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Tue, 8 Sep 2009 00:13:52 +0000 Subject: [PATCH] fix ComputeMaskedBits handling of zext/sext/trunc to work with vectors. This fixes PR4905 llvm-svn: 81174 --- llvm/lib/Analysis/ValueTracking.cpp | 15 +++++++++------ llvm/test/Transforms/InstCombine/crash.ll | 23 +++++++++++++++++++++-- 2 files changed, 30 insertions(+), 8 deletions(-) diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 78bb3dbc65d4..1782edee7bfc 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -232,12 +232,16 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask, // FALL THROUGH and handle them the same as zext/trunc. case Instruction::ZExt: case Instruction::Trunc: { + const Type *SrcTy = I->getOperand(0)->getType(); + + unsigned SrcBitWidth; // Note that we handle pointer operands here because of inttoptr/ptrtoint // which fall through here. - const Type *SrcTy = I->getOperand(0)->getType(); - unsigned SrcBitWidth = TD ? - TD->getTypeSizeInBits(SrcTy) : - SrcTy->getScalarSizeInBits(); + if (isa(SrcTy)) + SrcBitWidth = TD->getTypeSizeInBits(SrcTy); + else + SrcBitWidth = SrcTy->getScalarSizeInBits(); + APInt MaskIn(Mask); MaskIn.zextOrTrunc(SrcBitWidth); KnownZero.zextOrTrunc(SrcBitWidth); @@ -265,8 +269,7 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask, } case Instruction::SExt: { // Compute the bits in the result that are not present in the input. - const IntegerType *SrcTy = cast(I->getOperand(0)->getType()); - unsigned SrcBitWidth = SrcTy->getBitWidth(); + unsigned SrcBitWidth = I->getOperand(0)->getType()->getScalarSizeInBits(); APInt MaskIn(Mask); MaskIn.trunc(SrcBitWidth); diff --git a/llvm/test/Transforms/InstCombine/crash.ll b/llvm/test/Transforms/InstCombine/crash.ll index 03bad9924426..c252ac9dccf8 100644 --- a/llvm/test/Transforms/InstCombine/crash.ll +++ b/llvm/test/Transforms/InstCombine/crash.ll @@ -1,8 +1,8 @@ -; RUN: llvm-as < %s | opt -instcombine | llvm-dis +; RUN: opt < %s -instcombine | llvm-dis target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin10.0" -define i32 @_Z9model8bitR5Mixeri(i8 %tmp2) ssp { +define i32 @test0(i8 %tmp2) ssp { entry: %tmp3 = zext i8 %tmp2 to i32 %tmp8 = lshr i32 %tmp3, 6 @@ -12,3 +12,22 @@ entry: %tmp12 = xor i32 %tmp11, 0 ret i32 %tmp12 } + +; PR4905 +define <2 x i64> @test1(<2 x i64> %x, <2 x i64> %y) nounwind { +entry: + %conv.i94 = bitcast <2 x i64> %y to <4 x i32> ; <<4 x i32>> [#uses=1] + %sub.i97 = sub <4 x i32> %conv.i94, undef ; <<4 x i32>> [#uses=1] + %conv3.i98 = bitcast <4 x i32> %sub.i97 to <2 x i64> ; <<2 x i64>> [#uses=2] + %conv2.i86 = bitcast <2 x i64> %conv3.i98 to <4 x i32> ; <<4 x i32>> [#uses=1] + %cmp.i87 = icmp sgt <4 x i32> undef, %conv2.i86 ; <<4 x i1>> [#uses=1] + %sext.i88 = sext <4 x i1> %cmp.i87 to <4 x i32> ; <<4 x i32>> [#uses=1] + %conv3.i89 = bitcast <4 x i32> %sext.i88 to <2 x i64> ; <<2 x i64>> [#uses=1] + %and.i = and <2 x i64> %conv3.i89, %conv3.i98 ; <<2 x i64>> [#uses=1] + %or.i = or <2 x i64> zeroinitializer, %and.i ; <<2 x i64>> [#uses=1] + %conv2.i43 = bitcast <2 x i64> %or.i to <4 x i32> ; <<4 x i32>> [#uses=1] + %sub.i = sub <4 x i32> zeroinitializer, %conv2.i43 ; <<4 x i32>> [#uses=1] + %conv3.i44 = bitcast <4 x i32> %sub.i to <2 x i64> ; <<2 x i64>> [#uses=1] + ret <2 x i64> %conv3.i44 +} +