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[Hexagon] Adding postincrement register newvalue stores. 

llvm-svn: 225010
This commit is contained in:
Colin LeMahieu 2014-12-30 22:34:08 +00:00
parent 9014890819
commit 0cba5f1b43
2 changed files with 39 additions and 0 deletions
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30
llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -1312,6 +1312,36 @@ defm storerhnew: ST_PostInc_nv <"memh", "STrih", s4_1Imm, 0b01>;
let accessSize = WordAccess, isCodeGenOnly = 0 in let accessSize = WordAccess, isCodeGenOnly = 0 in
defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>; defm storerinew: ST_PostInc_nv <"memw", "STriw", s4_2Imm, 0b10>;
//===----------------------------------------------------------------------===//
// Template class for post increment .new stores with register offset
//===----------------------------------------------------------------------===//
let isNewValue = 1, mayStore = 1, isNVStore = 1, opNewValue = 3 in
class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
: NVInstPI_V4 <(outs IntRegs:$_dst_),
(ins IntRegs:$src1, ModRegs:$src2, IntRegs:$src3),
#mnemonic#"($src1++$src2) = $src3.new",
[], "$src1 = $_dst_"> {
bits<5> src1;
bits<1> src2;
bits<3> src3;
let accessSize = AccessSz;
let IClass = 0b1010;
let Inst{27-21} = 0b1101101;
let Inst{20-16} = src1;
let Inst{13} = src2;
let Inst{12-11} = MajOp;
let Inst{10-8} = src3;
let Inst{7} = 0b0;
}
let isCodeGenOnly = 0 in {
def S2_storerbnew_pr : T_StorePI_RegNV<"memb", 0b00, ByteAccess>;
def S2_storerhnew_pr : T_StorePI_RegNV<"memh", 0b01, HalfWordAccess>;
def S2_storerinew_pr : T_StorePI_RegNV<"memw", 0b10, WordAccess>;
}
// memb(Rx++#s4:0:circ(Mu))=Nt.new // memb(Rx++#s4:0:circ(Mu))=Nt.new
// memb(Rx++I:circ(Mu))=Nt.new // memb(Rx++I:circ(Mu))=Nt.new
// memb(Rx++Mu)=Nt.new // memb(Rx++Mu)=Nt.new

9
llvm/test/MC/Disassembler/Hexagon/nv_st.txt
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@ -9,6 +9,9 @@
0x1f 0x40 0x7f 0x70 0x28 0xc2 0xb1 0xab 0x1f 0x40 0x7f 0x70 0x28 0xc2 0xb1 0xab
# CHECK: r31 = r31 # CHECK: r31 = r31
# CHECK-NEXT: memb(r17++#5) = r2.new # CHECK-NEXT: memb(r17++#5) = r2.new
0x1f 0x40 0x7f 0x70 0x00 0xe2 0xb1 0xad
# CHECK: r31 = r31
# CHECK-NEXT: memb(r17++m1) = r2.new
0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34 0x1f 0x40 0x7f 0x70 0xe2 0xf5 0xb1 0x34
# CHECK: r31 = r31 # CHECK: r31 = r31
# CHECK-NEXT: if (p3) memb(r17+r21<<#3) = r2.new # CHECK-NEXT: if (p3) memb(r17+r21<<#3) = r2.new
@ -61,6 +64,9 @@
0x1f 0x40 0x7f 0x70 0x28 0xca 0xb1 0xab 0x1f 0x40 0x7f 0x70 0x28 0xca 0xb1 0xab
# CHECK: r31 = r31 # CHECK: r31 = r31
# CHECK-NEXT: memh(r17++#10) = r2.new # CHECK-NEXT: memh(r17++#10) = r2.new
0x1f 0x40 0x7f 0x70 0x00 0xea 0xb1 0xad
# CHECK: r31 = r31
# CHECK-NEXT: memh(r17++m1) = r2.new
0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34 0x1f 0x40 0x7f 0x70 0xea 0xf5 0xb1 0x34
# CHECK: r31 = r31 # CHECK: r31 = r31
# CHECK-NEXT: if (p3) memh(r17+r21<<#3) = r2.new # CHECK-NEXT: if (p3) memh(r17+r21<<#3) = r2.new
@ -113,6 +119,9 @@
0x1f 0x40 0x7f 0x70 0x28 0xd2 0xb1 0xab 0x1f 0x40 0x7f 0x70 0x28 0xd2 0xb1 0xab
# CHECK: r31 = r31 # CHECK: r31 = r31
# CHECK-NEXT: memw(r17++#20) = r2.new # CHECK-NEXT: memw(r17++#20) = r2.new
0x1f 0x40 0x7f 0x70 0x00 0xf2 0xb1 0xad
# CHECK: r31 = r31
# CHECK-NEXT: memw(r17++m1) = r2.new
0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34 0x1f 0x40 0x7f 0x70 0xf2 0xf5 0xb1 0x34
# CHECK: r31 = r31 # CHECK: r31 = r31
# CHECK-NEXT: if (p3) memw(r17+r21<<#3) = r2.new # CHECK-NEXT: if (p3) memw(r17+r21<<#3) = r2.new