forked from OSchip/llvm-project
[mips] Use 64-bit registers to return an sret pointer if target ABI is N64.
llvm-svn: 166344
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5d7e15edc5
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@ -3410,7 +3410,8 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain,
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if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
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unsigned Reg = MipsFI->getSRetReturnReg();
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if (!Reg) {
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Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
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Reg = MF.getRegInfo().
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createVirtualRegister(getRegClassFor(IsN64 ? MVT::i64 : MVT::i32));
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MipsFI->setSRetReturnReg(Reg);
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}
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SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
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@ -3539,7 +3540,8 @@ MipsTargetLowering::LowerReturn(SDValue Chain,
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llvm_unreachable("sret virtual register not created in the entry block");
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SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
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Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
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Chain = DAG.getCopyToReg(Chain, dl, IsN64 ? Mips::V0_64 : Mips::V0, Val,
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Flag);
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Flag = Chain.getValue(1);
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}
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@ -0,0 +1,14 @@
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; RUN: llc -march=mips64el -mcpu=mips64r2 -mattr=n64 -O0 < %s
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%struct.S = type { [8 x i32] }
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@g = common global %struct.S zeroinitializer, align 4
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define void @f(%struct.S* noalias sret %agg.result) nounwind {
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entry:
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%0 = bitcast %struct.S* %agg.result to i8*
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call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.S* @g to i8*), i64 32, i32 4, i1 false)
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ret void
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}
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declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
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