forked from OSchip/llvm-project
[AMDGPU] SOPxx instructions operand naming fixed in td files.
dst -> sdst ssrcN -> srcN Differential Revision: http://reviews.llvm.org/D17646 llvm-svn: 262801
This commit is contained in:
Valery Pykhtin
parent
581c0087b9
commit
0c6293da68
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@ -163,9 +163,9 @@ class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods
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class SOP1e <bits<8> op> : Enc32 {
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bits<7> sdst;
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bits<8> ssrc0;
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bits<8> src0;
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let Inst{7-0} = ssrc0;
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let Inst{7-0} = src0;
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let Inst{15-8} = op;
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let Inst{22-16} = sdst;
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let Inst{31-23} = 0x17d; //encoding;
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@ -173,22 +173,22 @@ class SOP1e <bits<8> op> : Enc32 {
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class SOP2e <bits<7> op> : Enc32 {
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bits<7> sdst;
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bits<8> ssrc0;
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bits<8> ssrc1;
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bits<8> src0;
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bits<8> src1;
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let Inst{7-0} = ssrc0;
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let Inst{15-8} = ssrc1;
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let Inst{7-0} = src0;
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let Inst{15-8} = src1;
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let Inst{22-16} = sdst;
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let Inst{29-23} = op;
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let Inst{31-30} = 0x2; // encoding
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}
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class SOPCe <bits<7> op> : Enc32 {
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bits<8> ssrc0;
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bits<8> ssrc1;
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bits<8> src0;
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bits<8> src1;
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let Inst{7-0} = ssrc0;
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let Inst{15-8} = ssrc1;
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let Inst{7-0} = src0;
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let Inst{15-8} = src1;
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let Inst{22-16} = op;
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let Inst{31-23} = 0x17e;
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}
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@ -820,27 +820,27 @@ multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
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}
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multiclass SOP1_32 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
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op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0),
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opName#" $dst, $src0", pattern
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op, opName, (outs SReg_32:$sdst), (ins SSrc_32:$src0),
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opName#" $sdst, $src0", pattern
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>;
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multiclass SOP1_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
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op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0),
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opName#" $dst, $src0", pattern
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op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0),
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opName#" $sdst, $src0", pattern
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>;
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// no input, 64-bit output.
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multiclass SOP1_64_0 <sop1 op, string opName, list<dag> pattern> {
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def "" : SOP1_Pseudo <opName, (outs SReg_64:$dst), (ins), pattern>;
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def "" : SOP1_Pseudo <opName, (outs SReg_64:$sdst), (ins), pattern>;
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def _si : SOP1_Real_si <op, opName, (outs SReg_64:$dst), (ins),
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opName#" $dst"> {
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let ssrc0 = 0;
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def _si : SOP1_Real_si <op, opName, (outs SReg_64:$sdst), (ins),
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opName#" $sdst"> {
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let src0 = 0;
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}
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def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$dst), (ins),
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opName#" $dst"> {
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let ssrc0 = 0;
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def _vi : SOP1_Real_vi <op, opName, (outs SReg_64:$sdst), (ins),
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opName#" $sdst"> {
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let src0 = 0;
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}
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}
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@ -861,8 +861,8 @@ multiclass SOP1_1 <sop1 op, string opName, list<dag> pattern> {
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// 64-bit input, 32-bit output.
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multiclass SOP1_32_64 <sop1 op, string opName, list<dag> pattern> : SOP1_m <
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op, opName, (outs SReg_32:$dst), (ins SSrc_64:$src0),
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opName#" $dst, $src0", pattern
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op, opName, (outs SReg_32:$sdst), (ins SSrc_64:$src0),
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opName#" $sdst, $src0", pattern
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>;
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class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
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@ -909,23 +909,23 @@ multiclass SOP2_m <sop2 op, string opName, dag outs, dag ins, string asm,
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}
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multiclass SOP2_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
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op, opName, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
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opName#" $dst, $src0, $src1", pattern
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op, opName, (outs SReg_32:$sdst), (ins SSrc_32:$src0, SSrc_32:$src1),
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opName#" $sdst, $src0, $src1", pattern
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>;
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multiclass SOP2_64 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
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op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1),
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opName#" $dst, $src0, $src1", pattern
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op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0, SSrc_64:$src1),
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opName#" $sdst, $src0, $src1", pattern
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>;
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multiclass SOP2_64_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
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op, opName, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_32:$src1),
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opName#" $dst, $src0, $src1", pattern
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op, opName, (outs SReg_64:$sdst), (ins SSrc_64:$src0, SSrc_32:$src1),
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opName#" $sdst, $src0, $src1", pattern
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>;
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multiclass SOP2_64_32_32 <sop2 op, string opName, list<dag> pattern> : SOP2_m <
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op, opName, (outs SReg_64:$dst), (ins SSrc_32:$src0, SSrc_32:$src1),
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opName#" $dst, $src0, $src1", pattern
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op, opName, (outs SReg_64:$sdst), (ins SSrc_32:$src0, SSrc_32:$src1),
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opName#" $sdst, $src0, $src1", pattern
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>;
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class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
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@ -980,14 +980,14 @@ multiclass SOPK_m <sopk op, string opName, dag outs, dag ins, string opAsm,
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}
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multiclass SOPK_32 <sopk op, string opName, list<dag> pattern> {
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def "" : SOPK_Pseudo <opName, (outs SReg_32:$dst), (ins u16imm:$src0),
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def "" : SOPK_Pseudo <opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
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pattern>;
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def _si : SOPK_Real_si <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
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opName#" $dst, $src0">;
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def _si : SOPK_Real_si <op, opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
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opName#" $sdst, $simm16">;
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def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$dst), (ins u16imm:$src0),
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opName#" $dst, $src0">;
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def _vi : SOPK_Real_vi <op, opName, (outs SReg_32:$sdst), (ins u16imm:$simm16),
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opName#" $sdst, $simm16">;
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}
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multiclass SOPK_SCC <sopk op, string opName, list<dag> pattern> {
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@ -119,11 +119,11 @@ let isMoveImm = 1 in {
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let Defs = [SCC] in {
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defm S_NOT_B32 : SOP1_32 <sop1<0x07, 0x04>, "s_not_b32",
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[(set i32:$dst, (not i32:$src0))]
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[(set i32:$sdst, (not i32:$src0))]
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>;
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defm S_NOT_B64 : SOP1_64 <sop1<0x08, 0x05>, "s_not_b64",
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[(set i64:$dst, (not i64:$src0))]
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[(set i64:$sdst, (not i64:$src0))]
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>;
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defm S_WQM_B32 : SOP1_32 <sop1<0x09, 0x06>, "s_wqm_b32", []>;
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defm S_WQM_B64 : SOP1_64 <sop1<0x0a, 0x07>, "s_wqm_b64", []>;
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@ -131,7 +131,7 @@ let Defs = [SCC] in {
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defm S_BREV_B32 : SOP1_32 <sop1<0x0b, 0x08>, "s_brev_b32",
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[(set i32:$dst, (bitreverse i32:$src0))]
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[(set i32:$sdst, (bitreverse i32:$src0))]
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>;
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defm S_BREV_B64 : SOP1_64 <sop1<0x0c, 0x09>, "s_brev_b64", []>;
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@ -139,7 +139,7 @@ let Defs = [SCC] in {
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defm S_BCNT0_I32_B32 : SOP1_32 <sop1<0x0d, 0x0a>, "s_bcnt0_i32_b32", []>;
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defm S_BCNT0_I32_B64 : SOP1_32_64 <sop1<0x0e, 0x0b>, "s_bcnt0_i32_b64", []>;
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defm S_BCNT1_I32_B32 : SOP1_32 <sop1<0x0f, 0x0c>, "s_bcnt1_i32_b32",
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[(set i32:$dst, (ctpop i32:$src0))]
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[(set i32:$sdst, (ctpop i32:$src0))]
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>;
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defm S_BCNT1_I32_B64 : SOP1_32_64 <sop1<0x10, 0x0d>, "s_bcnt1_i32_b64", []>;
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} // End Defs = [SCC]
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@ -147,24 +147,24 @@ let Defs = [SCC] in {
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defm S_FF0_I32_B32 : SOP1_32 <sop1<0x11, 0x0e>, "s_ff0_i32_b32", []>;
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defm S_FF0_I32_B64 : SOP1_32_64 <sop1<0x12, 0x0f>, "s_ff0_i32_b64", []>;
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defm S_FF1_I32_B32 : SOP1_32 <sop1<0x13, 0x10>, "s_ff1_i32_b32",
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[(set i32:$dst, (cttz_zero_undef i32:$src0))]
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[(set i32:$sdst, (cttz_zero_undef i32:$src0))]
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>;
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defm S_FF1_I32_B64 : SOP1_32_64 <sop1<0x14, 0x11>, "s_ff1_i32_b64", []>;
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defm S_FLBIT_I32_B32 : SOP1_32 <sop1<0x15, 0x12>, "s_flbit_i32_b32",
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[(set i32:$dst, (AMDGPUffbh_u32 i32:$src0))]
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[(set i32:$sdst, (AMDGPUffbh_u32 i32:$src0))]
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>;
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defm S_FLBIT_I32_B64 : SOP1_32_64 <sop1<0x16, 0x13>, "s_flbit_i32_b64", []>;
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defm S_FLBIT_I32 : SOP1_32 <sop1<0x17, 0x14>, "s_flbit_i32",
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[(set i32:$dst, (int_AMDGPU_flbit_i32 i32:$src0))]
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[(set i32:$sdst, (int_AMDGPU_flbit_i32 i32:$src0))]
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>;
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defm S_FLBIT_I32_I64 : SOP1_32_64 <sop1<0x18, 0x15>, "s_flbit_i32_i64", []>;
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defm S_SEXT_I32_I8 : SOP1_32 <sop1<0x19, 0x16>, "s_sext_i32_i8",
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[(set i32:$dst, (sext_inreg i32:$src0, i8))]
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[(set i32:$sdst, (sext_inreg i32:$src0, i8))]
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>;
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defm S_SEXT_I32_I16 : SOP1_32 <sop1<0x1a, 0x17>, "s_sext_i32_i16",
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[(set i32:$dst, (sext_inreg i32:$src0, i16))]
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[(set i32:$sdst, (sext_inreg i32:$src0, i16))]
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>;
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defm S_BITSET0_B32 : SOP1_32 <sop1<0x1b, 0x18>, "s_bitset0_b32", []>;
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@ -214,36 +214,36 @@ let Defs = [SCC] in { // Carry out goes to SCC
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let isCommutable = 1 in {
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defm S_ADD_U32 : SOP2_32 <sop2<0x00>, "s_add_u32", []>;
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defm S_ADD_I32 : SOP2_32 <sop2<0x02>, "s_add_i32",
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[(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))]
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[(set i32:$sdst, (add SSrc_32:$src0, SSrc_32:$src1))]
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>;
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} // End isCommutable = 1
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defm S_SUB_U32 : SOP2_32 <sop2<0x01>, "s_sub_u32", []>;
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defm S_SUB_I32 : SOP2_32 <sop2<0x03>, "s_sub_i32",
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[(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))]
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[(set i32:$sdst, (sub SSrc_32:$src0, SSrc_32:$src1))]
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>;
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let Uses = [SCC] in { // Carry in comes from SCC
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let isCommutable = 1 in {
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defm S_ADDC_U32 : SOP2_32 <sop2<0x04>, "s_addc_u32",
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[(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
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[(set i32:$sdst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
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} // End isCommutable = 1
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defm S_SUBB_U32 : SOP2_32 <sop2<0x05>, "s_subb_u32",
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[(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
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[(set i32:$sdst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>;
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} // End Uses = [SCC]
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defm S_MIN_I32 : SOP2_32 <sop2<0x06>, "s_min_i32",
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[(set i32:$dst, (smin i32:$src0, i32:$src1))]
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[(set i32:$sdst, (smin i32:$src0, i32:$src1))]
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>;
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defm S_MIN_U32 : SOP2_32 <sop2<0x07>, "s_min_u32",
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[(set i32:$dst, (umin i32:$src0, i32:$src1))]
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[(set i32:$sdst, (umin i32:$src0, i32:$src1))]
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>;
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defm S_MAX_I32 : SOP2_32 <sop2<0x08>, "s_max_i32",
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[(set i32:$dst, (smax i32:$src0, i32:$src1))]
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[(set i32:$sdst, (smax i32:$src0, i32:$src1))]
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>;
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defm S_MAX_U32 : SOP2_32 <sop2<0x09>, "s_max_u32",
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[(set i32:$dst, (umax i32:$src0, i32:$src1))]
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[(set i32:$sdst, (umax i32:$src0, i32:$src1))]
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>;
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} // End Defs = [SCC]
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@ -255,27 +255,27 @@ let Uses = [SCC] in {
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let Defs = [SCC] in {
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defm S_AND_B32 : SOP2_32 <sop2<0x0e, 0x0c>, "s_and_b32",
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[(set i32:$dst, (and i32:$src0, i32:$src1))]
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[(set i32:$sdst, (and i32:$src0, i32:$src1))]
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>;
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defm S_AND_B64 : SOP2_64 <sop2<0x0f, 0x0d>, "s_and_b64",
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[(set i64:$dst, (and i64:$src0, i64:$src1))]
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[(set i64:$sdst, (and i64:$src0, i64:$src1))]
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>;
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defm S_OR_B32 : SOP2_32 <sop2<0x10, 0x0e>, "s_or_b32",
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[(set i32:$dst, (or i32:$src0, i32:$src1))]
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[(set i32:$sdst, (or i32:$src0, i32:$src1))]
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>;
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defm S_OR_B64 : SOP2_64 <sop2<0x11, 0x0f>, "s_or_b64",
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[(set i64:$dst, (or i64:$src0, i64:$src1))]
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[(set i64:$sdst, (or i64:$src0, i64:$src1))]
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>;
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defm S_XOR_B32 : SOP2_32 <sop2<0x12, 0x10>, "s_xor_b32",
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[(set i32:$dst, (xor i32:$src0, i32:$src1))]
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[(set i32:$sdst, (xor i32:$src0, i32:$src1))]
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>;
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defm S_XOR_B64 : SOP2_64 <sop2<0x13, 0x11>, "s_xor_b64",
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[(set i64:$dst, (xor i64:$src0, i64:$src1))]
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[(set i64:$sdst, (xor i64:$src0, i64:$src1))]
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>;
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defm S_ANDN2_B32 : SOP2_32 <sop2<0x14, 0x12>, "s_andn2_b32", []>;
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defm S_ANDN2_B64 : SOP2_64 <sop2<0x15, 0x13>, "s_andn2_b64", []>;
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@ -294,30 +294,30 @@ let AddedComplexity = 1 in {
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let Defs = [SCC] in {
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defm S_LSHL_B32 : SOP2_32 <sop2<0x1e, 0x1c>, "s_lshl_b32",
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[(set i32:$dst, (shl i32:$src0, i32:$src1))]
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[(set i32:$sdst, (shl i32:$src0, i32:$src1))]
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>;
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defm S_LSHL_B64 : SOP2_64_32 <sop2<0x1f, 0x1d>, "s_lshl_b64",
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[(set i64:$dst, (shl i64:$src0, i32:$src1))]
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[(set i64:$sdst, (shl i64:$src0, i32:$src1))]
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>;
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defm S_LSHR_B32 : SOP2_32 <sop2<0x20, 0x1e>, "s_lshr_b32",
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[(set i32:$dst, (srl i32:$src0, i32:$src1))]
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[(set i32:$sdst, (srl i32:$src0, i32:$src1))]
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>;
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defm S_LSHR_B64 : SOP2_64_32 <sop2<0x21, 0x1f>, "s_lshr_b64",
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[(set i64:$dst, (srl i64:$src0, i32:$src1))]
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[(set i64:$sdst, (srl i64:$src0, i32:$src1))]
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>;
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defm S_ASHR_I32 : SOP2_32 <sop2<0x22, 0x20>, "s_ashr_i32",
|
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[(set i32:$dst, (sra i32:$src0, i32:$src1))]
|
||||
[(set i32:$sdst, (sra i32:$src0, i32:$src1))]
|
||||
>;
|
||||
defm S_ASHR_I64 : SOP2_64_32 <sop2<0x23, 0x21>, "s_ashr_i64",
|
||||
[(set i64:$dst, (sra i64:$src0, i32:$src1))]
|
||||
[(set i64:$sdst, (sra i64:$src0, i32:$src1))]
|
||||
>;
|
||||
} // End Defs = [SCC]
|
||||
|
||||
defm S_BFM_B32 : SOP2_32 <sop2<0x24, 0x22>, "s_bfm_b32",
|
||||
[(set i32:$dst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
|
||||
[(set i32:$sdst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
|
||||
defm S_BFM_B64 : SOP2_64_32_32 <sop2<0x25, 0x23>, "s_bfm_b64", []>;
|
||||
defm S_MUL_I32 : SOP2_32 <sop2<0x26, 0x24>, "s_mul_i32",
|
||||
[(set i32:$dst, (mul i32:$src0, i32:$src1))]
|
||||
[(set i32:$sdst, (mul i32:$src0, i32:$src1))]
|
||||
>;
|
||||
|
||||
} // End AddedComplexity = 1
|
||||
|
|
@ -513,7 +513,7 @@ def S_SLEEP : SOPP <0x0000000e, (ins i32imm:$simm16),
|
|||
let mayStore = 1;
|
||||
}
|
||||
|
||||
def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$sim16), "s_setprio $sim16">;
|
||||
def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$simm16), "s_setprio $simm16">;
|
||||
|
||||
let Uses = [EXEC, M0] in {
|
||||
// FIXME: Should this be mayLoad+mayStore?
|
||||
|
|
|
|||
Loading…
Reference in New Issue