forked from OSchip/llvm-project
parent
8429dbc753
commit
0c4fe2600a
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@ -726,7 +726,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
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}
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SmallVector<SUnit*, 2> Copies;
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InsertCCCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
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DOUT << "Adding an edge from SU # " << TrySU->NodeNum
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DOUT << "Adding an edge from SU #" << TrySU->NodeNum
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<< " to SU #" << Copies.front()->NodeNum << "\n";
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AddPred(TrySU, SDep(Copies.front(), SDep::Order, /*Latency=*/1,
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/*Reg=*/0, /*isNormalMemory=*/false,
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@ -735,7 +735,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
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NewDef = Copies.back();
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}
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DOUT << "Adding an edge from SU # " << NewDef->NodeNum
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DOUT << "Adding an edge from SU #" << NewDef->NodeNum
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<< " to SU #" << TrySU->NodeNum << "\n";
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LiveRegDefs[Reg] = NewDef;
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AddPred(NewDef, SDep(TrySU, SDep::Order, /*Latency=*/1,
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