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- Don't schedule nodes with only MVT::Flag and MVT::Other values for latency. 

- Compute CopyToReg use operand latency correctly.

llvm-svn: 117674
This commit is contained in:
Evan Cheng 2010-10-29 18:07:31 +00:00
parent 140542fcea
commit 0c4c5ca6e1
1 changed files with 7 additions and 3 deletions
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10
llvm/lib/Target/ARM/ARMISelLowering.cpp
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@ -855,6 +855,8 @@ Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
for (unsigned i = 0; i != NumVals; ++i) {
EVT VT = N->getValueType(i);
if (VT == MVT::Flag || VT == MVT::Other)
continue;
if (VT.isFloatingPoint() || VT.isVector())
return Sched::Latency;
}
@ -866,11 +868,13 @@ Sched::Preference ARMTargetLowering::getSchedulingPreference(SDNode *N) const {
// is not available.
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
if (TID.mayLoad())
if (TID.getNumDefs() == 0)
return Sched::RegPressure;
if (!Itins->isEmpty() &&
Itins->getOperandCycle(TID.getSchedClass(), 0) > 2)
return Sched::Latency;
if (!Itins->isEmpty() && Itins->getStageLatency(TID.getSchedClass()) > 2)
return Sched::Latency;
return Sched::RegPressure;
}