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Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the 

t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>

llvm-svn: 121417
This commit is contained in:
Bill Wendling 2010-12-09 21:49:07 +00:00
parent a3b23b025b
commit 0c4838bab7
3 changed files with 12 additions and 44 deletions
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6
llvm/lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -253,11 +253,7 @@ namespace {
const { return 0; }
uint32_t getAddrModeThumbSPOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
uint32_t getAddrModeS4OpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
uint32_t getAddrModeS2OpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
uint32_t getAddrModeS1OpValue(const MachineInstr &MI, unsigned Op)
uint32_t getAddrModeSOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
uint32_t getAddrModePCOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }

6
llvm/lib/Target/ARM/ARMInstrThumb.td
View File

@ -104,7 +104,7 @@ def t_addrmode_rr : Operand<i32>,
//
def t_addrmode_s4 : Operand<i32>,
ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
let EncoderMethod = "getAddrModeS4OpValue";
let EncoderMethod = "getAddrModeSOpValue";
let PrintMethod = "printThumbAddrModeS4Operand";
let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
let ParserMatchClass = MemModeThumbAsmOperand;
@ -115,7 +115,7 @@ def t_addrmode_s4 : Operand<i32>,
//
def t_addrmode_s2 : Operand<i32>,
ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
let EncoderMethod = "getAddrModeS2OpValue";
let EncoderMethod = "getAddrModeSOpValue";
let PrintMethod = "printThumbAddrModeS2Operand";
let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
let ParserMatchClass = MemModeThumbAsmOperand;
@ -126,7 +126,7 @@ def t_addrmode_s2 : Operand<i32>,
//
def t_addrmode_s1 : Operand<i32>,
ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
let EncoderMethod = "getAddrModeS1OpValue";
let EncoderMethod = "getAddrModeSOpValue";
let PrintMethod = "printThumbAddrModeS1Operand";
let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
let ParserMatchClass = MemModeThumbAsmOperand;

44
llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -178,17 +178,9 @@ public:
uint32_t getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands.
uint32_t getAddrModeS4OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getAddrModeS2OpValue - Return encoding for t_addrmode_s2 operands.
uint32_t getAddrModeS2OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getAddrModeS1OpValue - Return encoding for t_addrmode_s1 operands.
uint32_t getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
/// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
uint32_t getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &) const;
/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.
uint32_t getAddrModePCOpValue(const MCInst &MI, unsigned OpIdx,
@ -715,8 +707,9 @@ getAddrModeThumbSPOpValue(const MCInst &MI, unsigned OpIdx,
}
/// getAddrModeSOpValue - Encode the t_addrmode_s# operands.
static unsigned getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
unsigned Scale) {
uint32_t ARMMCCodeEmitter::
getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &) const {
// [Rn, Rm]
// {5-3} = Rm
// {2-0} = Rn
@ -728,34 +721,13 @@ static unsigned getAddrModeSOpValue(const MCInst &MI, unsigned OpIdx,
const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
const MCOperand &MO2 = MI.getOperand(OpIdx + 2);
unsigned Rn = getARMRegisterNumbering(MO.getReg());
unsigned Imm5 = (MO1.getImm() / Scale) & 0x1f;
unsigned Imm5 = MO1.getImm();
if (MO2.getReg() != 0)
// Is an immediate.
Imm5 = getARMRegisterNumbering(MO2.getReg());
return (Imm5 << 3) | Rn;
}
/// getAddrModeS4OpValue - Return encoding for t_addrmode_s4 operands.
uint32_t ARMMCCodeEmitter::
getAddrModeS4OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &) const {
return getAddrModeSOpValue(MI, OpIdx, 4);
}
/// getAddrModeS2OpValue - Return encoding for t_addrmode_s2 operands.
uint32_t ARMMCCodeEmitter::
getAddrModeS2OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &) const {
return getAddrModeSOpValue(MI, OpIdx, 2);
}
/// getAddrModeS1OpValue - Return encoding for t_addrmode_s1 operands.
uint32_t ARMMCCodeEmitter::
getAddrModeS1OpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &) const {
return getAddrModeSOpValue(MI, OpIdx, 1);
return ((Imm5 & 0x1f) << 3) | Rn;
}
/// getAddrModePCOpValue - Return encoding for t_addrmode_pc operands.