forked from OSchip/llvm-project
parent
8198db30f3
commit
0c45338961
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@ -30469,7 +30469,6 @@ static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG,
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"Unexpected shift opcode");
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"Unexpected shift opcode");
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bool LogicalShift = X86ISD::VSHLI == Opcode || X86ISD::VSRLI == Opcode;
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bool LogicalShift = X86ISD::VSHLI == Opcode || X86ISD::VSRLI == Opcode;
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EVT VT = N->getValueType(0);
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EVT VT = N->getValueType(0);
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unsigned NumElts = VT.getVectorNumElements();
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unsigned NumBitsPerElt = VT.getScalarSizeInBits();
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unsigned NumBitsPerElt = VT.getScalarSizeInBits();
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// This fails for mask register (vXi1) shifts.
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// This fails for mask register (vXi1) shifts.
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@ -30511,7 +30510,8 @@ static SDValue combineVectorShift(SDNode *N, SelectionDAG &DAG,
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SmallVector<APInt, 32> EltBits;
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SmallVector<APInt, 32> EltBits;
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if (N->isOnlyUserOf(N0.getNode()) &&
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if (N->isOnlyUserOf(N0.getNode()) &&
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getTargetConstantBitsFromNode(N0, NumBitsPerElt, UndefElts, EltBits)) {
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getTargetConstantBitsFromNode(N0, NumBitsPerElt, UndefElts, EltBits)) {
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assert(EltBits.size() == NumElts && "Unexpected shift value type");
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assert(EltBits.size() == VT.getVectorNumElements() &&
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"Unexpected shift value type");
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unsigned ShiftImm = ShiftVal.getZExtValue();
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unsigned ShiftImm = ShiftVal.getZExtValue();
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for (APInt &Elt : EltBits) {
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for (APInt &Elt : EltBits) {
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if (X86ISD::VSHLI == Opcode)
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if (X86ISD::VSHLI == Opcode)
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