forked from OSchip/llvm-project
fix PR8961 - a fast isel miscompilation where we'd insert a new instruction
after sext's generated for addressing that got folded. Previously we compiled test5 into: _test5: ## @test5 ## BB#0: movq -8(%rsp), %rax ## 8-byte Reload movq (%rdi,%rax), %rdi addq %rdx, %rdi movslq %esi, %rax movq %rax, -8(%rsp) ## 8-byte Spill movq %rdi, %rax ret which is insane and wrong. Now we produce: _test5: ## @test5 ## BB#0: movslq %esi, %rax movq (%rdi,%rax), %rax addq %rdx, %rax ret llvm-svn: 123414
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@ -1933,7 +1933,7 @@ bool X86FastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
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XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment);
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if (Result == 0) return false;
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MI->getParent()->insert(MI, Result);
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FuncInfo.MBB->insert(FuncInfo.InsertPt, Result);
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MI->eraseFromParent();
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return true;
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}
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@ -70,3 +70,20 @@ entry:
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; X64: test4:
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; X64: 128(%r{{.*}},%r{{.*}},8)
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}
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; PR8961 - Make sure the sext for the GEP addressing comes before the load that
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; is folded.
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define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind {
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%v8 = getelementptr i8* %A, i32 %I
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%v9 = bitcast i8* %v8 to i64*
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%v10 = load i64* %v9
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%v11 = add i64 %B, %v10
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ret i64 %v11
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; X64: test5:
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; X64: movslq %esi, %rax
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; X64-NEXT: movq (%rdi,%rax), %rax
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; X64-NEXT: addq %rdx, %rax
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; X64-NEXT: ret
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}
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