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Add intN vloadN() implementations for address spaces 3 and 4 

Not hooked up to R600 yet due to current lack of support, at least on EG.

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 188181
This commit is contained in:
Aaron Watry 2013-08-12 14:42:51 +00:00
parent c0aa6e0291
commit 0c21c7c747
1 changed files with 60 additions and 0 deletions
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60
libclc/generic/lib/shared/vload_impl.ll
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@ -61,6 +61,66 @@ define <16 x i32> @__clc_vload16_i32__addr2(i32 addrspace(2)* nocapture %addr) n
ret <16 x i32> %2
}
define <2 x i32> @__clc_vload2_i32__addr3(i32 addrspace(3)* nocapture %addr) nounwind readonly alwaysinline {
%1 = bitcast i32 addrspace(3)* %addr to <2 x i32> addrspace(3)*
%2 = load <2 x i32> addrspace(3)* %1, align 4, !tbaa !3
ret <2 x i32> %2
}
define <3 x i32> @__clc_vload3_i32__addr3(i32 addrspace(3)* nocapture %addr) nounwind readonly alwaysinline {
%1 = bitcast i32 addrspace(3)* %addr to <3 x i32> addrspace(3)*
%2 = load <3 x i32> addrspace(3)* %1, align 4, !tbaa !3
ret <3 x i32> %2
}
define <4 x i32> @__clc_vload4_i32__addr3(i32 addrspace(3)* nocapture %addr) nounwind readonly alwaysinline {
%1 = bitcast i32 addrspace(3)* %addr to <4 x i32> addrspace(3)*
%2 = load <4 x i32> addrspace(3)* %1, align 4, !tbaa !3
ret <4 x i32> %2
}
define <8 x i32> @__clc_vload8_i32__addr3(i32 addrspace(3)* nocapture %addr) nounwind readonly alwaysinline {
%1 = bitcast i32 addrspace(3)* %addr to <8 x i32> addrspace(3)*
%2 = load <8 x i32> addrspace(3)* %1, align 4, !tbaa !3
ret <8 x i32> %2
}
define <16 x i32> @__clc_vload16_i32__addr3(i32 addrspace(3)* nocapture %addr) nounwind readonly alwaysinline {
%1 = bitcast i32 addrspace(3)* %addr to <16 x i32> addrspace(3)*
%2 = load <16 x i32> addrspace(3)* %1, align 4, !tbaa !3
ret <16 x i32> %2
}
define <2 x i32> @__clc_vload2_i32__addr4(i32 addrspace(4)* nocapture %addr) nounwind readonly alwaysinline {
%1 = bitcast i32 addrspace(4)* %addr to <2 x i32> addrspace(4)*
%2 = load <2 x i32> addrspace(4)* %1, align 4, !tbaa !3
ret <2 x i32> %2
}
define <3 x i32> @__clc_vload3_i32__addr4(i32 addrspace(4)* nocapture %addr) nounwind readonly alwaysinline {
%1 = bitcast i32 addrspace(4)* %addr to <3 x i32> addrspace(4)*
%2 = load <3 x i32> addrspace(4)* %1, align 4, !tbaa !3
ret <3 x i32> %2
}
define <4 x i32> @__clc_vload4_i32__addr4(i32 addrspace(4)* nocapture %addr) nounwind readonly alwaysinline {
%1 = bitcast i32 addrspace(4)* %addr to <4 x i32> addrspace(4)*
%2 = load <4 x i32> addrspace(4)* %1, align 4, !tbaa !3
ret <4 x i32> %2
}
define <8 x i32> @__clc_vload8_i32__addr4(i32 addrspace(4)* nocapture %addr) nounwind readonly alwaysinline {
%1 = bitcast i32 addrspace(4)* %addr to <8 x i32> addrspace(4)*
%2 = load <8 x i32> addrspace(4)* %1, align 4, !tbaa !3
ret <8 x i32> %2
}
define <16 x i32> @__clc_vload16_i32__addr4(i32 addrspace(4)* nocapture %addr) nounwind readonly alwaysinline {
%1 = bitcast i32 addrspace(4)* %addr to <16 x i32> addrspace(4)*
%2 = load <16 x i32> addrspace(4)* %1, align 4, !tbaa !3
ret <16 x i32> %2
}
!1 = metadata !{metadata !"char", metadata !5}
!2 = metadata !{metadata !"short", metadata !5}
!3 = metadata !{metadata !"int", metadata !5}