forked from OSchip/llvm-project
Don't recalculate the loop info and loop dominators analyses if they're
preserved. llvm-svn: 45596
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@ -38,6 +38,14 @@ namespace llvm {
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FunctionPass *createMachineFunctionPrinterPass(std::ostream *OS,
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const std::string &Banner ="");
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/// MachineLoopInfo pass - This pass is a loop analysis pass.
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///
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extern const PassInfo *MachineLoopInfoID;
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/// MachineDominators pass - This pass is a machine dominators analysis pass.
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///
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extern const PassInfo *MachineDominatorsID;
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/// PHIElimination pass - This pass eliminates machine instruction PHI nodes
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/// by inserting copy instructions. This destroys SSA information, but is the
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/// desired input for some register allocators. This pass is "required" by
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@ -60,6 +60,8 @@ namespace {
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void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreserved<LiveVariables>();
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AU.addRequired<LiveVariables>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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AU.addPreservedID(PHIEliminationID);
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AU.addRequiredID(PHIEliminationID);
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AU.addRequiredID(TwoAddressInstructionPassID);
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@ -13,12 +13,17 @@
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/Passes.h"
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using namespace llvm;
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TEMPLATE_INSTANTIATION(class DomTreeNodeBase<MachineBasicBlock>);
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TEMPLATE_INSTANTIATION(class DominatorTreeBase<MachineBasicBlock>);
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char MachineDominatorTree::ID = 0;
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static RegisterPass<MachineDominatorTree>
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E("machinedomtree", "MachineDominator Tree Construction", true);
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namespace {
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char MachineDominatorTree::ID = 0;
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RegisterPass<MachineDominatorTree>
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E("machinedomtree", "MachineDominator Tree Construction", true);
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}
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const PassInfo *llvm::MachineDominatorsID = E.getPassInfo();
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@ -16,15 +16,20 @@
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/Passes.h"
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using namespace llvm;
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TEMPLATE_INSTANTIATION(class LoopBase<MachineBasicBlock>);
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TEMPLATE_INSTANTIATION(class LoopInfoBase<MachineBasicBlock>);
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char MachineLoopInfo::ID = 0;
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static RegisterPass<MachineLoopInfo>
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X("machine-loops", "Machine Natural Loop Construction", true);
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namespace {
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char MachineLoopInfo::ID = 0;
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RegisterPass<MachineLoopInfo>
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X("machine-loops", "Machine Natural Loop Construction", true);
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}
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const PassInfo *llvm::MachineLoopInfoID = X.getPassInfo();
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bool MachineLoopInfo::runOnMachineFunction(MachineFunction &) {
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releaseMemory();
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@ -51,6 +51,8 @@ namespace {
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreserved<LiveVariables>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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@ -104,6 +104,8 @@ namespace {
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// to coalescing and which analyses coalescing invalidates.
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AU.addRequiredTransitive<RegisterCoalescer>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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@ -67,6 +67,8 @@ const PassInfo *llvm::SimpleRegisterCoalescingID = X.getPassInfo();
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void SimpleRegisterCoalescing::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addPreserved<LiveIntervals>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addPreservedID(MachineDominatorsID);
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AU.addPreservedID(PHIEliminationID);
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AU.addPreservedID(TwoAddressInstructionPassID);
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AU.addRequired<LiveVariables>();
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@ -69,6 +69,8 @@ const PassInfo *llvm::TwoAddressInstructionPassID = X.getPassInfo();
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void TwoAddressInstructionPass::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveVariables>();
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AU.addPreserved<LiveVariables>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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AU.addPreservedID(PHIEliminationID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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