forked from OSchip/llvm-project
Implement AArch64 SISD intrinsics for vget_high and vget_low.
llvm-svn: 195074
This commit is contained in:
Jiangning Liu
parent
fe916e20f2
commit
0c0c1e8598
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@ -1590,16 +1590,31 @@ def Neon_High8H : PatFrag<(ops node:$in),
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(extract_subvector (v8i16 node:$in), (iPTR 4))>;
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def Neon_High4S : PatFrag<(ops node:$in),
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(extract_subvector (v4i32 node:$in), (iPTR 2))>;
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def Neon_High2D : PatFrag<(ops node:$in),
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(extract_subvector (v2i64 node:$in), (iPTR 1))>;
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def Neon_High4f : PatFrag<(ops node:$in),
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(extract_subvector (v4f32 node:$in), (iPTR 2))>;
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def Neon_High2d : PatFrag<(ops node:$in),
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(extract_subvector (v2f64 node:$in), (iPTR 1))>;
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def Neon_low16B : PatFrag<(ops node:$in),
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(v8i8 (extract_subvector (v16i8 node:$in),
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(iPTR 0)))>;
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def Neon_low8H : PatFrag<(ops node:$in),
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(v4i16 (extract_subvector (v8i16 node:$in),
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(iPTR 0)))>;
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def Neon_low4S : PatFrag<(ops node:$in),
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(v2i32 (extract_subvector (v4i32 node:$in),
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(iPTR 0)))>;
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def Neon_low2D : PatFrag<(ops node:$in),
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(v1i64 (extract_subvector (v2i64 node:$in),
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(iPTR 0)))>;
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def Neon_low4f : PatFrag<(ops node:$in),
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(v2f32 (extract_subvector (v4f32 node:$in),
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(iPTR 0)))>;
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def Neon_low2d : PatFrag<(ops node:$in),
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(v1f64 (extract_subvector (v2f64 node:$in),
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(iPTR 0)))>;
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def neon_uimm3_shift : Operand<i32>,
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ImmLeaf<i32, [{return Imm < 8;}]> {
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@ -5136,9 +5151,8 @@ def DUPdv_D : NeonI_Scalar_DUP<"dup", "d", FPR64, VPR128, neon_uimm1_bare> {
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multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
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ValueType OpTy, Operand OpImm,
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ValueType OpNTy, ValueType ExTy, Operand OpNImm> {
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def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
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(ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
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def : Pat<(ResTy (vector_extract (OpTy VPR128:$Rn), OpImm:$Imm)),
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(ResTy (DUPI (OpTy VPR128:$Rn), OpImm:$Imm))>;
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def : Pat<(ResTy (vector_extract (OpNTy VPR64:$Rn), OpNImm:$Imm)),
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(ResTy (DUPI
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@ -5146,6 +5160,21 @@ multiclass NeonI_Scalar_DUP_Elt_pattern<Instruction DUPI, ValueType ResTy,
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OpNImm:$Imm))>;
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}
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multiclass NeonI_SDUP<PatFrag GetLow, PatFrag GetHigh,
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ValueType ResTy, ValueType OpTy> {
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def : Pat<(ResTy (GetLow VPR128:$Rn)),
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(ResTy (DUPdv_D (OpTy VPR128:$Rn), 0))>;
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def : Pat<(ResTy (GetHigh VPR128:$Rn)),
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(ResTy (DUPdv_D (OpTy VPR128:$Rn), 1))>;
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}
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defm : NeonI_SDUP<Neon_low16B, Neon_High16B, v8i8, v16i8>;
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defm : NeonI_SDUP<Neon_low8H, Neon_High8H, v4i16, v8i16>;
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defm : NeonI_SDUP<Neon_low4S, Neon_High4S, v2i32, v4i32>;
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defm : NeonI_SDUP<Neon_low2D, Neon_High2D, v1i64, v2i64>;
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defm : NeonI_SDUP<Neon_low4f, Neon_High4f, v2f32, v4f32>;
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defm : NeonI_SDUP<Neon_low2d, Neon_High2d, v1f64, v2f64>;
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// Patterns for vector extract of FP data using scalar DUP instructions
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defm : NeonI_Scalar_DUP_Elt_pattern<DUPsv_S, f32,
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v4f32, neon_uimm2_bare, v2f32, v4f32, neon_uimm1_bare>;
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@ -0,0 +1,225 @@
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; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
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define <8 x i8> @test_vget_high_s8(<16 x i8> %a) {
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; CHECK: test_vget_high_s8:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i8> %shuffle.i
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}
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define <4 x i16> @test_vget_high_s16(<8 x i16> %a) {
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; CHECK: test_vget_high_s16:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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ret <4 x i16> %shuffle.i
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}
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define <2 x i32> @test_vget_high_s32(<4 x i32> %a) {
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; CHECK: test_vget_high_s32:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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ret <2 x i32> %shuffle.i
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}
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define <1 x i64> @test_vget_high_s64(<2 x i64> %a) {
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; CHECK: test_vget_high_s64:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> <i32 1>
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ret <1 x i64> %shuffle.i
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}
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define <8 x i8> @test_vget_high_u8(<16 x i8> %a) {
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; CHECK: test_vget_high_u8:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i8> %shuffle.i
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}
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define <4 x i16> @test_vget_high_u16(<8 x i16> %a) {
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; CHECK: test_vget_high_u16:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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ret <4 x i16> %shuffle.i
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}
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define <2 x i32> @test_vget_high_u32(<4 x i32> %a) {
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; CHECK: test_vget_high_u32:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
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ret <2 x i32> %shuffle.i
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}
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define <1 x i64> @test_vget_high_u64(<2 x i64> %a) {
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; CHECK: test_vget_high_u64:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> <i32 1>
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ret <1 x i64> %shuffle.i
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}
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define <1 x i64> @test_vget_high_p64(<2 x i64> %a) {
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; CHECK: test_vget_high_p64:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> <i32 1>
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ret <1 x i64> %shuffle.i
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}
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define <4 x i16> @test_vget_high_f16(<8 x i16> %a) {
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; CHECK: test_vget_high_f16:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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ret <4 x i16> %shuffle.i
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}
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define <2 x float> @test_vget_high_f32(<4 x float> %a) {
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; CHECK: test_vget_high_f32:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 2, i32 3>
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ret <2 x float> %shuffle.i
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}
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define <8 x i8> @test_vget_high_p8(<16 x i8> %a) {
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; CHECK: test_vget_high_p8:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
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ret <8 x i8> %shuffle.i
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}
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define <4 x i16> @test_vget_high_p16(<8 x i16> %a) {
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; CHECK: test_vget_high_p16:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
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ret <4 x i16> %shuffle.i
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}
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define <1 x double> @test_vget_high_f64(<2 x double> %a) {
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; CHECK: test_vget_high_f64:
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; CHECK: dup d0, {{v[0-9]+}}.d[1]
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entry:
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%shuffle.i = shufflevector <2 x double> %a, <2 x double> undef, <1 x i32> <i32 1>
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ret <1 x double> %shuffle.i
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}
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define <8 x i8> @test_vget_low_s8(<16 x i8> %a) {
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; CHECK: test_vget_low_s8:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i8> %shuffle.i
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}
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define <4 x i16> @test_vget_low_s16(<8 x i16> %a) {
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; CHECK: test_vget_low_s16:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i16> %shuffle.i
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}
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define <2 x i32> @test_vget_low_s32(<4 x i32> %a) {
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; CHECK: test_vget_low_s32:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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ret <2 x i32> %shuffle.i
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}
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define <1 x i64> @test_vget_low_s64(<2 x i64> %a) {
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; CHECK: test_vget_low_s64:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> zeroinitializer
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ret <1 x i64> %shuffle.i
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}
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define <8 x i8> @test_vget_low_u8(<16 x i8> %a) {
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; CHECK: test_vget_low_u8:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i8> %shuffle.i
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}
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define <4 x i16> @test_vget_low_u16(<8 x i16> %a) {
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; CHECK: test_vget_low_u16:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i16> %shuffle.i
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}
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define <2 x i32> @test_vget_low_u32(<4 x i32> %a) {
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; CHECK: test_vget_low_u32:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <4 x i32> %a, <4 x i32> undef, <2 x i32> <i32 0, i32 1>
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ret <2 x i32> %shuffle.i
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}
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define <1 x i64> @test_vget_low_u64(<2 x i64> %a) {
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; CHECK: test_vget_low_u64:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> zeroinitializer
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ret <1 x i64> %shuffle.i
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}
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define <1 x i64> @test_vget_low_p64(<2 x i64> %a) {
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; CHECK: test_vget_low_p64:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <2 x i64> %a, <2 x i64> undef, <1 x i32> zeroinitializer
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ret <1 x i64> %shuffle.i
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}
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define <4 x i16> @test_vget_low_f16(<8 x i16> %a) {
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; CHECK: test_vget_low_f16:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i16> %shuffle.i
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}
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define <2 x float> @test_vget_low_f32(<4 x float> %a) {
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; CHECK: test_vget_low_f32:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <4 x float> %a, <4 x float> undef, <2 x i32> <i32 0, i32 1>
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ret <2 x float> %shuffle.i
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}
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define <8 x i8> @test_vget_low_p8(<16 x i8> %a) {
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; CHECK: test_vget_low_p8:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x i8> %shuffle.i
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}
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define <4 x i16> @test_vget_low_p16(<8 x i16> %a) {
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; CHECK: test_vget_low_p16:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x i16> %shuffle.i
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}
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define <1 x double> @test_vget_low_f64(<2 x double> %a) {
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; CHECK: test_vget_low_f64:
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; CHECK: dup d0, {{v[0-9]+}}.d[0]
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entry:
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%shuffle.i = shufflevector <2 x double> %a, <2 x double> undef, <1 x i32> zeroinitializer
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ret <1 x double> %shuffle.i
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}
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