forked from OSchip/llvm-project
[X86] Improve mul combine for negative multiplayer (2^c - 1)
This patch improves the mul instruction combine function (combineMul) by adding new layer of logic. In this patch, we are adding the ability to fold (mul x, -((1 << c) -1)) or (mul x, -((1 << c) +1)) into (neg(X << c) -x) or (neg((x << c) + x) respective. Differential Revision: https://reviews.llvm.org/D28232 llvm-svn: 292358
This commit is contained in:
Michael Zuckerman
parent
03c5e69d07
commit
0c0240ce84
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@ -30256,22 +30256,37 @@ static SDValue combineMul(SDNode *N, SelectionDAG &DAG,
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}
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if (!NewMul) {
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assert(MulAmt != 0 && MulAmt != (VT == MVT::i64 ? UINT64_MAX : UINT32_MAX)
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&& "Both cases that could cause potential overflows should have "
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"already been handled.");
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if (isPowerOf2_64(MulAmt - 1))
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// (mul x, 2^N + 1) => (add (shl x, N), x)
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NewMul = DAG.getNode(ISD::ADD, DL, VT, N->getOperand(0),
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DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
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DAG.getConstant(Log2_64(MulAmt - 1), DL,
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MVT::i8)));
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else if (isPowerOf2_64(MulAmt + 1))
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// (mul x, 2^N - 1) => (sub (shl x, N), x)
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NewMul = DAG.getNode(ISD::SUB, DL, VT, DAG.getNode(ISD::SHL, DL, VT,
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N->getOperand(0),
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DAG.getConstant(Log2_64(MulAmt + 1),
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DL, MVT::i8)), N->getOperand(0));
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assert(MulAmt != 0 &&
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MulAmt != (VT == MVT::i64 ? UINT64_MAX : UINT32_MAX) &&
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"Both cases that could cause potential overflows should have "
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"already been handled.");
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int64_t SignMulAmt = C->getSExtValue();
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if ((SignMulAmt != INT64_MIN) && (SignMulAmt != INT64_MAX) &&
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(SignMulAmt != -INT64_MAX)) {
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int NumSign = SignMulAmt > 0 ? 1 : -1;
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bool IsPowerOf2_64PlusOne = isPowerOf2_64(NumSign * SignMulAmt - 1);
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bool IsPowerOf2_64MinusOne = isPowerOf2_64(NumSign * SignMulAmt + 1);
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if (IsPowerOf2_64PlusOne) {
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// (mul x, 2^N + 1) => (add (shl x, N), x)
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NewMul = DAG.getNode(
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ISD::ADD, DL, VT, N->getOperand(0),
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DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
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DAG.getConstant(Log2_64(NumSign * SignMulAmt - 1), DL,
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MVT::i8)));
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} else if (IsPowerOf2_64MinusOne) {
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// (mul x, 2^N - 1) => (sub (shl x, N), x)
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NewMul = DAG.getNode(
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ISD::SUB, DL, VT,
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DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0),
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DAG.getConstant(Log2_64(NumSign * SignMulAmt + 1), DL,
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MVT::i8)),
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N->getOperand(0));
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}
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// To negate, subtract the number from zero
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if ((IsPowerOf2_64PlusOne || IsPowerOf2_64MinusOne) && NumSign == -1)
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NewMul =
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DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), NewMul);
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}
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}
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if (NewMul)
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@ -171,3 +171,233 @@ define i64 @mul18446744073709551615_64(i64 %A) {
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%mul = mul i64 %A, 18446744073709551615
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ret i64 %mul
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}
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define i32 @test(i32 %a) {
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; X64-LABEL: test:
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; X64: # BB#0: # %entry
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: shll $5, %eax
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; X64-NEXT: subl %edi, %eax
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; X64-NEXT: retq
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;
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; X86-LABEL: test:
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; X86: # BB#0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: shll $5, %eax
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; X86-NEXT: subl %ecx, %eax
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; X86-NEXT: retl
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entry:
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%tmp3 = mul i32 %a, 31
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ret i32 %tmp3
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}
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define i32 @test1(i32 %a) {
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; X64-LABEL: test1:
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; X64: # BB#0: # %entry
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: shll $5, %eax
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; X64-NEXT: subl %edi, %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: retq
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;
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; X86-LABEL: test1:
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; X86: # BB#0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: shll $5, %eax
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; X86-NEXT: subl %ecx, %eax
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; X86-NEXT: negl %eax
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; X86-NEXT: retl
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entry:
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%tmp3 = mul i32 %a, -31
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ret i32 %tmp3
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}
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define i32 @test2(i32 %a) {
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; X64-LABEL: test2:
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; X64: # BB#0: # %entry
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; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: shll $5, %eax
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; X64-NEXT: leal (%rax,%rdi), %eax
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; X64-NEXT: retq
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;
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; X86-LABEL: test2:
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; X86: # BB#0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: shll $5, %eax
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; X86-NEXT: addl %ecx, %eax
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; X86-NEXT: retl
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entry:
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%tmp3 = mul i32 %a, 33
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ret i32 %tmp3
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}
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define i32 @test3(i32 %a) {
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; X64-LABEL: test3:
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; X64: # BB#0: # %entry
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; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: shll $5, %eax
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; X64-NEXT: leal (%rax,%rdi), %eax
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; X64-NEXT: negl %eax
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; X64-NEXT: retq
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;
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; X86-LABEL: test3:
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; X86: # BB#0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: shll $5, %eax
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; X86-NEXT: addl %ecx, %eax
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; X86-NEXT: negl %eax
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; X86-NEXT: retl
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entry:
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%tmp3 = mul i32 %a, -33
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ret i32 %tmp3
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}
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define i64 @test4(i64 %a) {
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; X64-LABEL: test4:
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; X64: # BB#0: # %entry
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: shlq $5, %rax
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; X64-NEXT: subq %rdi, %rax
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; X64-NEXT: retq
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;
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; X86-LABEL: test4:
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; X86: # BB#0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: shll $5, %ecx
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; X86-NEXT: subl %eax, %ecx
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; X86-NEXT: movl $31, %eax
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; X86-NEXT: mull {{[0-9]+}}(%esp)
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; X86-NEXT: addl %ecx, %edx
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; X86-NEXT: retl
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entry:
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%tmp3 = mul i64 %a, 31
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ret i64 %tmp3
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}
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define i64 @test5(i64 %a) {
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; X64-LABEL: test5:
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; X64: # BB#0: # %entry
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: shlq $5, %rax
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; X64-NEXT: subq %rdi, %rax
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; X64-NEXT: negq %rax
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; X64-NEXT: retq
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;
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; X86-LABEL: test5:
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; X86: # BB#0: # %entry
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; X86-NEXT: pushl %esi
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; X86-NEXT: .Lcfi0:
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: .Lcfi1:
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; X86-NEXT: .cfi_offset %esi, -8
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl %eax, %esi
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; X86-NEXT: shll $5, %esi
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; X86-NEXT: subl %eax, %esi
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; X86-NEXT: movl $-31, %edx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: mull %edx
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; X86-NEXT: subl %ecx, %edx
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; X86-NEXT: subl %esi, %edx
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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entry:
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%tmp3 = mul i64 %a, -31
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ret i64 %tmp3
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}
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define i64 @test6(i64 %a) {
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; X64-LABEL: test6:
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; X64: # BB#0: # %entry
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: shlq $5, %rax
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; X64-NEXT: leaq (%rax,%rdi), %rax
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; X64-NEXT: retq
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;
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; X86-LABEL: test6:
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; X86: # BB#0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: shll $5, %ecx
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; X86-NEXT: addl %eax, %ecx
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; X86-NEXT: movl $33, %eax
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; X86-NEXT: mull {{[0-9]+}}(%esp)
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; X86-NEXT: addl %ecx, %edx
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; X86-NEXT: retl
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entry:
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%tmp3 = mul i64 %a, 33
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ret i64 %tmp3
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}
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define i64 @test7(i64 %a) {
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; X64-LABEL: test7:
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; X64: # BB#0: # %entry
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: shlq $5, %rax
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; X64-NEXT: leaq (%rax,%rdi), %rax
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; X64-NEXT: negq %rax
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; X64-NEXT: retq
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;
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; X86-LABEL: test7:
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; X86: # BB#0: # %entry
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; X86-NEXT: pushl %esi
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; X86-NEXT: .Lcfi2:
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: .Lcfi3:
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; X86-NEXT: .cfi_offset %esi, -8
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl %eax, %esi
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; X86-NEXT: shll $5, %esi
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; X86-NEXT: addl %eax, %esi
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; X86-NEXT: movl $-33, %edx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: mull %edx
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; X86-NEXT: subl %ecx, %edx
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; X86-NEXT: subl %esi, %edx
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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entry:
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%tmp3 = mul i64 %a, -33
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ret i64 %tmp3
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}
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define i64 @testOverflow(i64 %a) {
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; X64-LABEL: testOverflow:
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; X64: # BB#0: # %entry
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; X64-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
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; X64-NEXT: imulq %rdi, %rax
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; X64-NEXT: retq
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;
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; X86-LABEL: testOverflow:
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; X86: # BB#0: # %entry
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; X86-NEXT: pushl %esi
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; X86-NEXT: .Lcfi4:
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: .Lcfi5:
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; X86-NEXT: .cfi_offset %esi, -8
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl $-1, %edx
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; X86-NEXT: movl %ecx, %eax
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; X86-NEXT: mull %edx
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; X86-NEXT: movl %ecx, %esi
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; X86-NEXT: shll $31, %esi
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; X86-NEXT: subl %ecx, %esi
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; X86-NEXT: addl %esi, %edx
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; X86-NEXT: subl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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entry:
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%tmp3 = mul i64 %a, 9223372036854775807
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ret i64 %tmp3
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}
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