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R600/SI: Add definition for S_CBRANCH_G_FORK 

llvm-svn: 229686
This commit is contained in:
Tom Stellard 2015-02-18 16:08:13 +00:00
parent ce449ade7e
commit 0c0008cb6e
2 changed files with 13 additions and 1 deletions
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6
llvm/lib/Target/R600/SIInstrInfo.td
View File

@ -454,6 +454,12 @@ class SOP2_Pseudo<string opName, dag outs, dag ins, list<dag> pattern> :
SIMCInstr<opName, SISubtarget.NONE> {
let isPseudo = 1;
let Size = 4;
// Pseudo instructions have no encodings, but adding this field here allows
// us to do:
// let sdst = xxx in {
// for multiclasses that include both real and pseudo instructions.
field bits<7> sdst = 0;
}
class SOP2_Real_si<sop2 op, string opName, dag outs, dag ins, string asm> :

8
llvm/lib/Target/R600/SIInstructions.td
View File

@ -319,7 +319,13 @@ defm S_BFE_U64 : SOP2_64 <sop2<0x29, 0x27>, "s_bfe_u64", []>;
defm S_BFE_I64 : SOP2_64_32 <sop2<0x2a, 0x28>, "s_bfe_i64", []>;
} // End Defs = [SCC]
//defm S_CBRANCH_G_FORK : SOP2_ <sop2<0x2b, 0x29>, "s_cbranch_g_fork", []>;
let sdst = 0 in {
defm S_CBRANCH_G_FORK : SOP2_m <
sop2<0x2b, 0x29>, "s_cbranch_g_fork", (outs),
(ins SReg_64:$src0, SReg_64:$src1), "s_cbranch_g_fork $src0, $src1", []
>;
}
let Defs = [SCC] in {
defm S_ABSDIFF_I32 : SOP2_32 <sop2<0x2c, 0x2a>, "s_absdiff_i32", []>;
} // End Defs = [SCC]