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[AMDGPU][MC] Corrected error position for swizzle() 

Partially fixes bug 47518 (https://bugs.llvm.org/show_bug.cgi?id=47518)

Reviewers: rampitec

Differential Revision: https://reviews.llvm.org/D91408
This commit is contained in:
Dmitry Preobrazhensky 2020-11-16 14:37:57 +03:00
parent 89df8fc0d7
commit 0bee8c784b
2 changed files with 61 additions and 27 deletions
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76
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
View File

@ -1419,6 +1419,11 @@ public:
OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
OperandMatchResultTy parseBoolReg(OperandVector &Operands);
bool parseSwizzleOperand(int64_t &Op,
const unsigned MinVal,
const unsigned MaxVal,
const StringRef ErrMsg,
SMLoc &Loc);
bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
const unsigned MinVal,
const unsigned MaxVal,
@ -6091,23 +6096,36 @@ encodeBitmaskPerm(const unsigned AndMask,
(XorMask << BITMASK_XOR_SHIFT);
}
bool
AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op,
const unsigned MinVal,
const unsigned MaxVal,
const StringRef ErrMsg,
SMLoc &Loc) {
if (!skipToken(AsmToken::Comma, "expected a comma")) {
return false;
}
Loc = Parser.getTok().getLoc();
if (!parseExpr(Op)) {
return false;
}
if (Op < MinVal || Op > MaxVal) {
Error(Loc, ErrMsg);
return false;
}
return true;
}
bool
AMDGPUAsmParser::parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
const unsigned MinVal,
const unsigned MaxVal,
const StringRef ErrMsg) {
SMLoc Loc;
for (unsigned i = 0; i < OpNum; ++i) {
if (!skipToken(AsmToken::Comma, "expected a comma")){
if (!parseSwizzleOperand(Op[i], MinVal, MaxVal, ErrMsg, Loc))
return false;
}
SMLoc ExprLoc = Parser.getTok().getLoc();
if (!parseExpr(Op[i])) {
return false;
}
if (Op[i] < MinVal || Op[i] > MaxVal) {
Error(ExprLoc, ErrMsg);
return false;
}
}
return true;
@ -6133,22 +6151,24 @@ bool
AMDGPUAsmParser::parseSwizzleBroadcast(int64_t &Imm) {
using namespace llvm::AMDGPU::Swizzle;
SMLoc S = Parser.getTok().getLoc();
SMLoc Loc;
int64_t GroupSize;
int64_t LaneIdx;
if (!parseSwizzleOperands(1, &GroupSize,
2, 32,
"group size must be in the interval [2,32]")) {
if (!parseSwizzleOperand(GroupSize,
2, 32,
"group size must be in the interval [2,32]",
Loc)) {
return false;
}
if (!isPowerOf2_64(GroupSize)) {
Error(S, "group size must be a power of two");
Error(Loc, "group size must be a power of two");
return false;
}
if (parseSwizzleOperands(1, &LaneIdx,
0, GroupSize - 1,
"lane id must be in the interval [0,group size - 1]")) {
if (parseSwizzleOperand(LaneIdx,
0, GroupSize - 1,
"lane id must be in the interval [0,group size - 1]",
Loc)) {
Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0);
return true;
}
@ -6159,15 +6179,17 @@ bool
AMDGPUAsmParser::parseSwizzleReverse(int64_t &Imm) {
using namespace llvm::AMDGPU::Swizzle;
SMLoc S = Parser.getTok().getLoc();
SMLoc Loc;
int64_t GroupSize;
if (!parseSwizzleOperands(1, &GroupSize,
2, 32, "group size must be in the interval [2,32]")) {
if (!parseSwizzleOperand(GroupSize,
2, 32,
"group size must be in the interval [2,32]",
Loc)) {
return false;
}
if (!isPowerOf2_64(GroupSize)) {
Error(S, "group size must be a power of two");
Error(Loc, "group size must be a power of two");
return false;
}
@ -6179,15 +6201,17 @@ bool
AMDGPUAsmParser::parseSwizzleSwap(int64_t &Imm) {
using namespace llvm::AMDGPU::Swizzle;
SMLoc S = Parser.getTok().getLoc();
SMLoc Loc;
int64_t GroupSize;
if (!parseSwizzleOperands(1, &GroupSize,
1, 16, "group size must be in the interval [1,16]")) {
if (!parseSwizzleOperand(GroupSize,
1, 16,
"group size must be in the interval [1,16]",
Loc)) {
return false;
}
if (!isPowerOf2_64(GroupSize)) {
Error(S, "group size must be a power of two");
Error(Loc, "group size must be a power of two");
return false;
}

12
llvm/test/MC/AMDGPU/gfx10_err_pos.s
View File

@ -429,7 +429,17 @@ s_mov_b64 s[10:11], s[1:0]
ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1)
// CHECK: error: group size must be a power of two
// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(BROADCAST,3,1)
// CHECK-NEXT:{{^}} ^
// CHECK-NEXT:{{^}} ^
ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)
// CHECK: error: group size must be a power of two
// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(REVERSE,3)
// CHECK-NEXT:{{^}} ^
ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3)
// CHECK: error: group size must be a power of two
// CHECK-NEXT:{{^}}ds_swizzle_b32 v8, v2 offset:swizzle(SWAP,3)
// CHECK-NEXT:{{^}} ^
//==============================================================================
// group size must be in the interval [1,16]