forked from OSchip/llvm-project
[Tests] Highlight impact of multiple exit LFTR (D62625) as requested by reviewer
llvm-svn: 363217
This commit is contained in:
Philip Reames
parent
189abad128
commit
0bded8442f
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@ -274,3 +274,161 @@ latch:
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exit:
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ret void
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}
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;; Show the value of multiple exit LFTR (being able to eliminate all but
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;; one IV when exit tests involve multiple IVs).
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define void @combine_ivs(i32 %n) {
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; CHECK-LABEL: @combine_ivs(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 1, [[ENTRY]] ], [ [[IV2_NEXT:%.*]], [[LATCH]] ]
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; CHECK-NEXT: [[EARLYCND:%.*]] = icmp ult i32 [[IV]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EARLYCND]], label [[LATCH]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: [[IV2_NEXT]] = add nuw nsw i32 [[IV2]], 1
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; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV2_NEXT]], 1000
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; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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%iv2 = phi i32 [ 1, %entry], [ %iv2.next, %latch]
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%earlycnd = icmp ult i32 %iv, %n
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br i1 %earlycnd, label %latch, label %exit
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latch:
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%iv.next = add i32 %iv, 1
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%iv2.next = add i32 %iv2, 1
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store volatile i32 %iv, i32* @A
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%c = icmp ult i32 %iv2.next, 1000
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br i1 %c, label %loop, label %exit
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exit:
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ret void
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}
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; We can remove the decrementing IV entirely
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define void @combine_ivs2(i32 %n) {
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; CHECK-LABEL: @combine_ivs2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[IV2:%.*]] = phi i32 [ 1000, [[ENTRY]] ], [ [[IV2_NEXT:%.*]], [[LATCH]] ]
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; CHECK-NEXT: [[EARLYCND:%.*]] = icmp ult i32 [[IV]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EARLYCND]], label [[LATCH]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: [[IV2_NEXT]] = sub nuw nsw i32 [[IV2]], 1
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; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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; CHECK-NEXT: [[C:%.*]] = icmp ugt i32 [[IV2_NEXT]], 0
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; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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%iv2 = phi i32 [ 1000, %entry], [ %iv2.next, %latch]
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%earlycnd = icmp ult i32 %iv, %n
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br i1 %earlycnd, label %latch, label %exit
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latch:
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%iv.next = add i32 %iv, 1
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%iv2.next = sub i32 %iv2, 1
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store volatile i32 %iv, i32* @A
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%c = icmp ugt i32 %iv2.next, 0
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br i1 %c, label %loop, label %exit
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exit:
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ret void
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}
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; An example where we can eliminate an f(i) computation entirely
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; from a multiple exit loop with LFTR.
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define void @simplify_exit_test(i32 %n) {
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; CHECK-LABEL: @simplify_exit_test(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[EARLYCND:%.*]] = icmp ult i32 [[IV]], [[N:%.*]]
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; CHECK-NEXT: br i1 [[EARLYCND]], label [[LATCH]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: [[FX:%.*]] = shl i32 [[IV]], 4
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; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[FX]], 1024
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; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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%earlycnd = icmp ult i32 %iv, %n
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br i1 %earlycnd, label %latch, label %exit
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latch:
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%iv.next = add i32 %iv, 1
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%fx = shl i32 %iv, 4
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store volatile i32 %iv, i32* @A
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%c = icmp ult i32 %fx, 1024
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br i1 %c, label %loop, label %exit
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exit:
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ret void
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}
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; Another example where we can remove an f(i) type computation, but this
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; time in a loop w/o a statically computable exit count.
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define void @simplify_exit_test2(i32 %n) {
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; CHECK-LABEL: @simplify_exit_test2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ]
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; CHECK-NEXT: [[VOL:%.*]] = load volatile i32, i32* @A
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; CHECK-NEXT: [[EARLYCND:%.*]] = icmp ne i32 [[VOL]], 0
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; CHECK-NEXT: br i1 [[EARLYCND]], label [[LATCH]], label [[EXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[FX:%.*]] = udiv i32 [[IV]], 4
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; CHECK-NEXT: store volatile i32 [[IV]], i32* @A
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; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[FX]], 1024
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; CHECK-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry], [ %iv.next, %latch]
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%vol = load volatile i32, i32* @A
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%earlycnd = icmp ne i32 %vol, 0
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br i1 %earlycnd, label %latch, label %exit
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latch:
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%iv.next = add i32 %iv, 1
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%fx = udiv i32 %iv, 4
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store volatile i32 %iv, i32* @A
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%c = icmp ult i32 %fx, 1024
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br i1 %c, label %loop, label %exit
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exit:
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ret void
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}
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