forked from OSchip/llvm-project
[X86] For AVX1/AVX2 isel, don't use FP move instructions for 128-bit loads/stores of integer types.
For SSE we use fp because of the smaller encoding, but that doesn't apply to AVX. So just do the natural thing so we don't have to explain why we aren't. We can't do this for 256-bit loads/stores since integer loads and stores aren't available in AVX1 so we need fallback patterns since the integer types are legal. This doesn't affect any tests because execution domain fixing freely converts the instructions anyway. Honestly, we could probably rely on it for the SSE size optimization too. llvm-svn: 293743
This commit is contained in:
Craig Topper
parent
9dd2ff4604
commit
0bcba19cdf
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@ -954,24 +954,10 @@ let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
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IIC_SSE_MOVU_P_RR>;
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}
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// Use vmovaps/vmovups for AVX integer load/store.
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let Predicates = [HasAVX, NoVLX] in {
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// 128-bit load/store
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def : Pat<(alignedloadv2i64 addr:$src),
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(VMOVAPSrm addr:$src)>;
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def : Pat<(loadv2i64 addr:$src),
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(VMOVUPSrm addr:$src)>;
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def : Pat<(alignedstore (v2i64 VR128:$src), addr:$dst),
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(VMOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
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(VMOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v2i64 VR128:$src), addr:$dst),
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(VMOVUPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v4i32 VR128:$src), addr:$dst),
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(VMOVUPSmr addr:$dst, VR128:$src)>;
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// 256-bit load/store
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// 256-bit load/store need to use floating point load/store in case we don't
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// have AVX2. Execution domain fixing will convert to integer if AVX2 is
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// available and changing the domain is beneficial.
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def : Pat<(alignedloadv4i64 addr:$src),
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(VMOVAPSYrm addr:$src)>;
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def : Pat<(loadv4i64 addr:$src),
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@ -980,10 +966,18 @@ let Predicates = [HasAVX, NoVLX] in {
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(VMOVAPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(alignedstore256 (v8i32 VR256:$src), addr:$dst),
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(VMOVAPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
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(VMOVAPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
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(VMOVAPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(store (v4i64 VR256:$src), addr:$dst),
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(VMOVUPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(store (v8i32 VR256:$src), addr:$dst),
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(VMOVUPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(store (v16i16 VR256:$src), addr:$dst),
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(VMOVUPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(store (v32i8 VR256:$src), addr:$dst),
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(VMOVUPSYmr addr:$dst, VR256:$src)>;
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// Special patterns for storing subvector extracts of lower 128-bits
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// Its cheaper to just use VMOVAPS/VMOVUPS instead of VEXTRACTF128mr
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@ -993,18 +987,6 @@ let Predicates = [HasAVX, NoVLX] in {
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def : Pat<(alignedstore (v4f32 (extract_subvector
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(v8f32 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v2i64 (extract_subvector
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(v4i64 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVAPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v4i32 (extract_subvector
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(v8i32 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v8i16 (extract_subvector
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(v16i16 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v16i8 (extract_subvector
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(v32i8 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVAPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v2f64 (extract_subvector
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(v4f64 VR256:$src), (iPTR 0))), addr:$dst),
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@ -1012,40 +994,6 @@ let Predicates = [HasAVX, NoVLX] in {
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def : Pat<(store (v4f32 (extract_subvector
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(v8f32 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVUPSmr addr:$dst, (v4f32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v2i64 (extract_subvector
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(v4i64 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVUPDmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v4i32 (extract_subvector
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(v8i32 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVUPSmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v8i16 (extract_subvector
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(v16i16 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVUPSmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v16i8 (extract_subvector
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(v32i8 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVUPSmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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}
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let Predicates = [HasAVX, NoVLX] in {
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// 128-bit load/store
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def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
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(VMOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
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(VMOVAPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v8i16 VR128:$src), addr:$dst),
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(VMOVUPSmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v16i8 VR128:$src), addr:$dst),
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(VMOVUPSmr addr:$dst, VR128:$src)>;
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// 256-bit load/store
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def : Pat<(alignedstore256 (v16i16 VR256:$src), addr:$dst),
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(VMOVAPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(alignedstore256 (v32i8 VR256:$src), addr:$dst),
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(VMOVAPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(store (v16i16 VR256:$src), addr:$dst),
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(VMOVUPSYmr addr:$dst, VR256:$src)>;
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def : Pat<(store (v32i8 VR256:$src), addr:$dst),
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(VMOVUPSYmr addr:$dst, VR256:$src)>;
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}
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// Use movaps / movups for SSE integer load / store (one byte shorter).
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@ -3853,40 +3801,44 @@ def VMOVDQUYrr_REV : VSSI<0x7F, MRMDestReg, (outs VR256:$dst), (ins VR256:$src),
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let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1,
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hasSideEffects = 0, SchedRW = [WriteLoad] in {
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let Predicates = [HasAVX,NoVLX] in
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def VMOVDQArm : VPDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
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VEX;
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"movdqa\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (alignedloadv2i64 addr:$src))],
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IIC_SSE_MOVA_P_RM>, VEX;
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def VMOVDQAYrm : VPDI<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
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"movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RM>,
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VEX, VEX_L;
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let Predicates = [HasAVX] in {
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def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
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XS, VEX;
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def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
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"vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
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XS, VEX, VEX_L;
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}
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let Predicates = [HasAVX,NoVLX] in
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def VMOVDQUrm : I<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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"vmovdqu\t{$src, $dst|$dst, $src}",
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[(set VR128:$dst, (loadv2i64 addr:$src))],
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IIC_SSE_MOVU_P_RM>, XS, VEX;
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def VMOVDQUYrm : I<0x6F, MRMSrcMem, (outs VR256:$dst), (ins i256mem:$src),
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"vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_RM>,
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XS, VEX, VEX_L;
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}
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let mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in {
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let Predicates = [HasAVX,NoVLX] in
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def VMOVDQAmr : VPDI<0x7F, MRMDestMem, (outs),
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(ins i128mem:$dst, VR128:$src),
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"movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
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VEX;
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"movdqa\t{$src, $dst|$dst, $src}",
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[(alignedstore (v2i64 VR128:$src), addr:$dst)],
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IIC_SSE_MOVA_P_MR>, VEX;
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def VMOVDQAYmr : VPDI<0x7F, MRMDestMem, (outs),
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(ins i256mem:$dst, VR256:$src),
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"movdqa\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_MR>,
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VEX, VEX_L;
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let Predicates = [HasAVX] in {
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let Predicates = [HasAVX,NoVLX] in
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def VMOVDQUmr : I<0x7F, MRMDestMem, (outs), (ins i128mem:$dst, VR128:$src),
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"vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
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"vmovdqu\t{$src, $dst|$dst, $src}",
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[(store (v2i64 VR128:$src), addr:$dst)], IIC_SSE_MOVU_P_MR>,
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XS, VEX;
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def VMOVDQUYmr : I<0x7F, MRMDestMem, (outs), (ins i256mem:$dst, VR256:$src),
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"vmovdqu\t{$src, $dst|$dst, $src}",[], IIC_SSE_MOVU_P_MR>,
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XS, VEX, VEX_L;
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}
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}
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let SchedRW = [WriteMove] in {
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let hasSideEffects = 0 in {
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@ -3948,6 +3900,50 @@ def : InstAlias<"vmovdqu\t{$src, $dst|$dst, $src}",
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def : InstAlias<"vmovdqu\t{$src, $dst|$dst, $src}",
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(VMOVDQUYrr_REV VR256L:$dst, VR256H:$src), 0>;
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let Predicates = [HasAVX, NoVLX] in {
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// Additional patterns for other integer sizes.
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def : Pat<(alignedstore (v4i32 VR128:$src), addr:$dst),
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(VMOVDQAmr addr:$dst, VR128:$src)>;
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def : Pat<(alignedstore (v8i16 VR128:$src), addr:$dst),
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(VMOVDQAmr addr:$dst, VR128:$src)>;
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def : Pat<(alignedstore (v16i8 VR128:$src), addr:$dst),
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(VMOVDQAmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v4i32 VR128:$src), addr:$dst),
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(VMOVDQUmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v8i16 VR128:$src), addr:$dst),
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(VMOVDQUmr addr:$dst, VR128:$src)>;
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def : Pat<(store (v16i8 VR128:$src), addr:$dst),
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(VMOVDQUmr addr:$dst, VR128:$src)>;
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// Special patterns for storing subvector extracts of lower 128-bits
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// Its cheaper to just use VMOVDQA/VMOVDQU instead of VEXTRACTF128mr
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def : Pat<(alignedstore (v2i64 (extract_subvector
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(v4i64 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVDQAmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v4i32 (extract_subvector
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(v8i32 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVDQAmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v8i16 (extract_subvector
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(v16i16 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVDQAmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(alignedstore (v16i8 (extract_subvector
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(v32i8 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVDQAmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v2i64 (extract_subvector
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(v4i64 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVDQUmr addr:$dst, (v2i64 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v4i32 (extract_subvector
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(v8i32 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVDQUmr addr:$dst, (v4i32 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v8i16 (extract_subvector
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(v16i16 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVDQUmr addr:$dst, (v8i16 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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def : Pat<(store (v16i8 (extract_subvector
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(v32i8 VR256:$src), (iPTR 0))), addr:$dst),
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(VMOVDQUmr addr:$dst, (v16i8 (EXTRACT_SUBREG VR256:$src,sub_xmm)))>;
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}
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//===---------------------------------------------------------------------===//
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// SSE2 - Packed Integer Arithmetic Instructions
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//===---------------------------------------------------------------------===//
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