forked from OSchip/llvm-project
[AMDGPU] Tweak some compares in wqm.ll test
This prevents the compares from being optimized away when D86578 lands, which seems unintended. Also fixed some unused results.
This commit is contained in:
Jay Foad
parent
d6b0734837
commit
0bc14a0a98
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@ -360,7 +360,7 @@ define amdgpu_ps float @test_wwm3(i32 inreg %idx) {
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; GFX9-W64: ; %bb.0: ; %main_body
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; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX9-W64-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 32, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0
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; GFX9-W64-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-W64-NEXT: s_and_saveexec_b64 s[2:3], vcc
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; GFX9-W64-NEXT: s_cbranch_execz .LBB9_2
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@ -381,7 +381,7 @@ define amdgpu_ps float @test_wwm3(i32 inreg %idx) {
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; GFX10-W32: ; %bb.0: ; %main_body
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; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX10-W32-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 32, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 16, v0
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; GFX10-W32-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
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; GFX10-W32-NEXT: s_cbranch_execz .LBB9_2
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@ -401,7 +401,7 @@ main_body:
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; use mbcnt to make sure the branch is divergent
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
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%cc = icmp uge i32 %hi, 32
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%cc = icmp uge i32 %hi, 16
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br i1 %cc, label %endif, label %if
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if:
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@ -425,7 +425,7 @@ define amdgpu_ps float @test_wwm4(i32 inreg %idx) {
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; GFX9-W64: ; %bb.0: ; %main_body
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; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX9-W64-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 32, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0
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; GFX9-W64-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-W64-NEXT: s_and_saveexec_b64 s[2:3], vcc
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; GFX9-W64-NEXT: s_cbranch_execz .LBB10_2
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@ -445,7 +445,7 @@ define amdgpu_ps float @test_wwm4(i32 inreg %idx) {
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; GFX10-W32: ; %bb.0: ; %main_body
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; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX10-W32-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 32, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 16, v0
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; GFX10-W32-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
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; GFX10-W32-NEXT: s_cbranch_execz .LBB10_2
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@ -464,7 +464,7 @@ main_body:
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; use mbcnt to make sure the branch is divergent
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
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%cc = icmp uge i32 %hi, 32
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%cc = icmp uge i32 %hi, 16
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br i1 %cc, label %endif, label %if
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if:
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@ -548,7 +548,7 @@ define amdgpu_ps float @test_wwm6_then() {
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; GFX9-W64-NEXT: s_mov_b64 exec, s[0:1]
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; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX9-W64-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 32, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0
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; GFX9-W64-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-W64-NEXT: s_and_saveexec_b64 s[0:1], vcc
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; GFX9-W64-NEXT: s_cbranch_execz .LBB12_2
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@ -571,7 +571,7 @@ define amdgpu_ps float @test_wwm6_then() {
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; GFX10-W32-NEXT: s_mov_b32 exec_lo, s0
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; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX10-W32-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 32, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 16, v0
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; GFX10-W32-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-W32-NEXT: s_and_saveexec_b32 s0, vcc_lo
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; GFX10-W32-NEXT: s_cbranch_execz .LBB12_2
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@ -590,7 +590,7 @@ main_body:
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; use mbcnt to make sure the branch is divergent
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
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%cc = icmp uge i32 %hi, 32
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%cc = icmp uge i32 %hi, 16
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br i1 %cc, label %endif, label %if
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if:
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@ -617,7 +617,8 @@ define amdgpu_ps float @test_wwm6_loop() {
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; GFX9-W64-NEXT: global_load_dword v1, v[3:4], off glc
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; GFX9-W64-NEXT: s_waitcnt vmcnt(0)
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; GFX9-W64-NEXT: s_mov_b64 exec, s[0:1]
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; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v3, -1, 0
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; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX9-W64-NEXT: v_mbcnt_hi_u32_b32 v3, -1, v0
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; GFX9-W64-NEXT: s_mov_b64 s[0:1], 0
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; GFX9-W64-NEXT: .LBB13_1: ; %loop
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; GFX9-W64-NEXT: ; =>This Inner Loop Header: Depth=1
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@ -644,8 +645,9 @@ define amdgpu_ps float @test_wwm6_loop() {
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; GFX10-W32-NEXT: global_load_dword v1, v[3:4], off glc dlc
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; GFX10-W32-NEXT: s_waitcnt vmcnt(0)
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; GFX10-W32-NEXT: s_mov_b32 exec_lo, s0
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; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v3, -1, 0
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; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX10-W32-NEXT: s_mov_b32 s0, 0
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; GFX10-W32-NEXT: v_mbcnt_hi_u32_b32 v3, -1, v0
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; GFX10-W32-NEXT: .LBB13_1: ; %loop
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; GFX10-W32-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX10-W32-NEXT: s_or_saveexec_b32 s1, -1
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@ -672,7 +674,7 @@ main_body:
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br label %loop
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loop:
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%counter = phi i32 [ %lo, %main_body ], [ %counter.1, %loop ]
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%counter = phi i32 [ %hi, %main_body ], [ %counter.1, %loop ]
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%src1 = load volatile float, float addrspace(1)* undef
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%out = fadd float %src0, %src1
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%out.0 = call float @llvm.amdgcn.wwm.f32(float %out)
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@ -817,7 +819,7 @@ define amdgpu_ps float @test_strict_wqm3(i32 inreg %idx) {
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; GFX9-W64: ; %bb.0: ; %main_body
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; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX9-W64-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 32, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0
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; GFX9-W64-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-W64-NEXT: s_and_saveexec_b64 s[2:3], vcc
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; GFX9-W64-NEXT: s_cbranch_execz .LBB17_2
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@ -839,7 +841,7 @@ define amdgpu_ps float @test_strict_wqm3(i32 inreg %idx) {
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; GFX10-W32: ; %bb.0: ; %main_body
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; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX10-W32-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 32, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 16, v0
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; GFX10-W32-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
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; GFX10-W32-NEXT: s_cbranch_execz .LBB17_2
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@ -860,7 +862,7 @@ main_body:
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; use mbcnt to make sure the branch is divergent
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
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%cc = icmp uge i32 %hi, 32
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%cc = icmp uge i32 %hi, 16
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br i1 %cc, label %endif, label %if
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if:
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@ -884,7 +886,7 @@ define amdgpu_ps float @test_strict_wqm4(i32 inreg %idx) {
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; GFX9-W64: ; %bb.0: ; %main_body
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; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX9-W64-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 32, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0
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; GFX9-W64-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-W64-NEXT: s_and_saveexec_b64 s[2:3], vcc
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; GFX9-W64-NEXT: s_cbranch_execz .LBB18_2
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@ -905,7 +907,7 @@ define amdgpu_ps float @test_strict_wqm4(i32 inreg %idx) {
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; GFX10-W32: ; %bb.0: ; %main_body
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; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX10-W32-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 32, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 16, v0
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; GFX10-W32-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
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; GFX10-W32-NEXT: s_cbranch_execz .LBB18_2
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@ -925,7 +927,7 @@ main_body:
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; use mbcnt to make sure the branch is divergent
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
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%cc = icmp uge i32 %hi, 32
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%cc = icmp uge i32 %hi, 16
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br i1 %cc, label %endif, label %if
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if:
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@ -1013,7 +1015,7 @@ define amdgpu_ps float @test_strict_wqm6_then() {
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; GFX9-W64-NEXT: s_mov_b64 exec, s[0:1]
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; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX9-W64-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 32, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0
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; GFX9-W64-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-W64-NEXT: s_and_saveexec_b64 s[0:1], vcc
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; GFX9-W64-NEXT: s_cbranch_execz .LBB20_2
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@ -1038,7 +1040,7 @@ define amdgpu_ps float @test_strict_wqm6_then() {
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; GFX10-W32-NEXT: s_mov_b32 exec_lo, s0
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; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX10-W32-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 32, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 16, v0
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; GFX10-W32-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-W32-NEXT: s_and_saveexec_b32 s0, vcc_lo
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; GFX10-W32-NEXT: s_cbranch_execz .LBB20_2
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@ -1058,7 +1060,7 @@ main_body:
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; use mbcnt to make sure the branch is divergent
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
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%cc = icmp uge i32 %hi, 32
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%cc = icmp uge i32 %hi, 16
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br i1 %cc, label %endif, label %if
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if:
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@ -1086,7 +1088,8 @@ define amdgpu_ps float @test_strict_wqm6_loop() {
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; GFX9-W64-NEXT: global_load_dword v1, v[3:4], off glc
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; GFX9-W64-NEXT: s_waitcnt vmcnt(0)
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; GFX9-W64-NEXT: s_mov_b64 exec, s[0:1]
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; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v3, -1, 0
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; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX9-W64-NEXT: v_mbcnt_hi_u32_b32 v3, -1, v0
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; GFX9-W64-NEXT: s_mov_b64 s[0:1], 0
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; GFX9-W64-NEXT: .LBB21_1: ; %loop
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; GFX9-W64-NEXT: ; =>This Inner Loop Header: Depth=1
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@ -1116,8 +1119,9 @@ define amdgpu_ps float @test_strict_wqm6_loop() {
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; GFX10-W32-NEXT: global_load_dword v1, v[3:4], off glc dlc
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; GFX10-W32-NEXT: s_waitcnt vmcnt(0)
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; GFX10-W32-NEXT: s_mov_b32 exec_lo, s0
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; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v3, -1, 0
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; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX10-W32-NEXT: s_mov_b32 s0, 0
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; GFX10-W32-NEXT: v_mbcnt_hi_u32_b32 v3, -1, v0
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; GFX10-W32-NEXT: .LBB21_1: ; %loop
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; GFX10-W32-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX10-W32-NEXT: s_mov_b32 s1, exec_lo
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@ -1146,7 +1150,7 @@ main_body:
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br label %loop
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loop:
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%counter = phi i32 [ %lo, %main_body ], [ %counter.1, %loop ]
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%counter = phi i32 [ %hi, %main_body ], [ %counter.1, %loop ]
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%src1 = load volatile float, float addrspace(1)* undef
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%out = fadd float %src0, %src1
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%out.0 = call float @llvm.amdgcn.strict.wqm.f32(float %out)
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@ -2464,7 +2468,7 @@ define amdgpu_ps float @test_strict_wwm3(i32 inreg %idx) {
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; GFX9-W64: ; %bb.0: ; %main_body
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; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX9-W64-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 32, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0
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; GFX9-W64-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-W64-NEXT: s_and_saveexec_b64 s[2:3], vcc
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; GFX9-W64-NEXT: s_cbranch_execz .LBB39_2
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@ -2485,7 +2489,7 @@ define amdgpu_ps float @test_strict_wwm3(i32 inreg %idx) {
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; GFX10-W32: ; %bb.0: ; %main_body
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; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX10-W32-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 32, v0
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; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 16, v0
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; GFX10-W32-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
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; GFX10-W32-NEXT: s_cbranch_execz .LBB39_2
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@ -2505,7 +2509,7 @@ main_body:
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; use mbcnt to make sure the branch is divergent
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%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
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%hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
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%cc = icmp uge i32 %hi, 32
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%cc = icmp uge i32 %hi, 16
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br i1 %cc, label %endif, label %if
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if:
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@ -2529,7 +2533,7 @@ define amdgpu_ps float @test_strict_wwm4(i32 inreg %idx) {
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; GFX9-W64: ; %bb.0: ; %main_body
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; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GFX9-W64-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
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; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 32, v0
|
||||
; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0
|
||||
; GFX9-W64-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX9-W64-NEXT: s_and_saveexec_b64 s[2:3], vcc
|
||||
; GFX9-W64-NEXT: s_cbranch_execz .LBB40_2
|
||||
|
|
@ -2549,7 +2553,7 @@ define amdgpu_ps float @test_strict_wwm4(i32 inreg %idx) {
|
|||
; GFX10-W32: ; %bb.0: ; %main_body
|
||||
; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
|
||||
; GFX10-W32-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
|
||||
; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 32, v0
|
||||
; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 16, v0
|
||||
; GFX10-W32-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX10-W32-NEXT: s_and_saveexec_b32 s1, vcc_lo
|
||||
; GFX10-W32-NEXT: s_cbranch_execz .LBB40_2
|
||||
|
|
@ -2568,7 +2572,7 @@ main_body:
|
|||
; use mbcnt to make sure the branch is divergent
|
||||
%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
|
||||
%hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
|
||||
%cc = icmp uge i32 %hi, 32
|
||||
%cc = icmp uge i32 %hi, 16
|
||||
br i1 %cc, label %endif, label %if
|
||||
|
||||
if:
|
||||
|
|
@ -2652,7 +2656,7 @@ define amdgpu_ps float @test_strict_wwm6_then() {
|
|||
; GFX9-W64-NEXT: s_mov_b64 exec, s[0:1]
|
||||
; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
|
||||
; GFX9-W64-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
|
||||
; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 32, v0
|
||||
; GFX9-W64-NEXT: v_cmp_gt_u32_e32 vcc, 16, v0
|
||||
; GFX9-W64-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX9-W64-NEXT: s_and_saveexec_b64 s[0:1], vcc
|
||||
; GFX9-W64-NEXT: s_cbranch_execz .LBB42_2
|
||||
|
|
@ -2675,7 +2679,7 @@ define amdgpu_ps float @test_strict_wwm6_then() {
|
|||
; GFX10-W32-NEXT: s_mov_b32 exec_lo, s0
|
||||
; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
|
||||
; GFX10-W32-NEXT: v_mbcnt_hi_u32_b32 v0, -1, v0
|
||||
; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 32, v0
|
||||
; GFX10-W32-NEXT: v_cmp_gt_u32_e32 vcc_lo, 16, v0
|
||||
; GFX10-W32-NEXT: v_mov_b32_e32 v0, 0
|
||||
; GFX10-W32-NEXT: s_and_saveexec_b32 s0, vcc_lo
|
||||
; GFX10-W32-NEXT: s_cbranch_execz .LBB42_2
|
||||
|
|
@ -2694,7 +2698,7 @@ main_body:
|
|||
; use mbcnt to make sure the branch is divergent
|
||||
%lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0)
|
||||
%hi = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %lo)
|
||||
%cc = icmp uge i32 %hi, 32
|
||||
%cc = icmp uge i32 %hi, 16
|
||||
br i1 %cc, label %endif, label %if
|
||||
|
||||
if:
|
||||
|
|
@ -2717,7 +2721,8 @@ define amdgpu_ps float @test_strict_wwm6_loop() {
|
|||
; GFX9-W64-NEXT: global_load_dword v1, v[3:4], off glc
|
||||
; GFX9-W64-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX9-W64-NEXT: s_mov_b64 exec, s[0:1]
|
||||
; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v3, -1, 0
|
||||
; GFX9-W64-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
|
||||
; GFX9-W64-NEXT: v_mbcnt_hi_u32_b32 v3, -1, v0
|
||||
; GFX9-W64-NEXT: s_mov_b64 s[0:1], 0
|
||||
; GFX9-W64-NEXT: .LBB43_1: ; %loop
|
||||
; GFX9-W64-NEXT: ; =>This Inner Loop Header: Depth=1
|
||||
|
|
@ -2744,8 +2749,9 @@ define amdgpu_ps float @test_strict_wwm6_loop() {
|
|||
; GFX10-W32-NEXT: global_load_dword v1, v[3:4], off glc dlc
|
||||
; GFX10-W32-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-W32-NEXT: s_mov_b32 exec_lo, s0
|
||||
; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v3, -1, 0
|
||||
; GFX10-W32-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
|
||||
; GFX10-W32-NEXT: s_mov_b32 s0, 0
|
||||
; GFX10-W32-NEXT: v_mbcnt_hi_u32_b32 v3, -1, v0
|
||||
; GFX10-W32-NEXT: .LBB43_1: ; %loop
|
||||
; GFX10-W32-NEXT: ; =>This Inner Loop Header: Depth=1
|
||||
; GFX10-W32-NEXT: s_or_saveexec_b32 s1, -1
|
||||
|
|
@ -2772,7 +2778,7 @@ main_body:
|
|||
br label %loop
|
||||
|
||||
loop:
|
||||
%counter = phi i32 [ %lo, %main_body ], [ %counter.1, %loop ]
|
||||
%counter = phi i32 [ %hi, %main_body ], [ %counter.1, %loop ]
|
||||
%src1 = load volatile float, float addrspace(1)* undef
|
||||
%out = fadd float %src0, %src1
|
||||
%out.0 = call float @llvm.amdgcn.strict.wwm.f32(float %out)
|
||||
|
|
|
|||
Loading…
Reference in New Issue