forked from OSchip/llvm-project
Use KILL instead of IMPLICIT_DEF in LowerSubregs pass.
llvm-svn: 83007
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@ -126,11 +126,10 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
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if (SrcReg == DstReg) {
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if (SrcReg == DstReg) {
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// No need to insert an identity copy instruction.
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// No need to insert an identity copy instruction.
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if (MI->getOperand(1).isKill()) {
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if (MI->getOperand(1).isKill()) {
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// We must make sure the super-register gets killed.Replace the
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// We must make sure the super-register gets killed. Replace the
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// instruction with IMPLICIT_DEF.
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// instruction with KILL.
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MI->setDesc(TII.get(TargetInstrInfo::IMPLICIT_DEF));
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MI->setDesc(TII.get(TargetInstrInfo::KILL));
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MI->RemoveOperand(2); // SubIdx
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MI->RemoveOperand(2); // SubIdx
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MI->getOperand(1).setImplicit(true);
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DEBUG(errs() << "subreg: replace by: " << *MI);
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DEBUG(errs() << "subreg: replace by: " << *MI);
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return true;
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return true;
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}
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}
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@ -243,14 +242,14 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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if (DstSubReg == InsReg) {
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if (DstSubReg == InsReg) {
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// No need to insert an identity copy instruction. If the SrcReg was
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// No need to insert an identity copy instruction. If the SrcReg was
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// <undef>, we need to make sure it is alive by inserting an IMPLICIT_DEF
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// <undef>, we need to make sure it is alive by inserting a KILL
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if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
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if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
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MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
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MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
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TII.get(TargetInstrInfo::IMPLICIT_DEF), DstReg);
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TII.get(TargetInstrInfo::KILL), DstReg);
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if (MI->getOperand(2).isUndef())
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if (MI->getOperand(2).isUndef())
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MIB.addReg(InsReg, RegState::Implicit | RegState::Undef);
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MIB.addReg(InsReg, RegState::Undef);
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else
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else
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MIB.addReg(InsReg, RegState::ImplicitKill);
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MIB.addReg(InsReg, RegState::Kill);
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} else {
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} else {
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DEBUG(errs() << "subreg: eliminated!\n");
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DEBUG(errs() << "subreg: eliminated!\n");
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MBB->erase(MI);
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MBB->erase(MI);
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@ -261,10 +260,10 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
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const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
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const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg);
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const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
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const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg);
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if (MI->getOperand(2).isUndef())
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if (MI->getOperand(2).isUndef())
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// If the source register being inserted is undef, then this becomes an
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// If the source register being inserted is undef, then this becomes a
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// implicit_def.
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// KILL.
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BuildMI(*MBB, MI, MI->getDebugLoc(),
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BuildMI(*MBB, MI, MI->getDebugLoc(),
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TII.get(TargetInstrInfo::IMPLICIT_DEF), DstSubReg);
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TII.get(TargetInstrInfo::KILL), DstSubReg);
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else
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else
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TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
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TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
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MachineBasicBlock::iterator CopyMI = MI;
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MachineBasicBlock::iterator CopyMI = MI;
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@ -655,11 +655,11 @@ bool SchedulePostRATDList::BreakAntiDependencies() {
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I != E; --Count) {
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I != E; --Count) {
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MachineInstr *MI = --I;
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MachineInstr *MI = --I;
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// After regalloc, IMPLICIT_DEF instructions aren't safe to treat as
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// After regalloc, KILL instructions aren't safe to treat as
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// dependence-breaking. In the case of an INSERT_SUBREG, the IMPLICIT_DEF
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// dependence-breaking. In the case of an INSERT_SUBREG, the KILL
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// is left behind appearing to clobber the super-register, while the
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// is left behind appearing to clobber the super-register, while the
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// subregister needs to remain live. So we just ignore them.
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// subregister needs to remain live. So we just ignore them.
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if (MI->getOpcode() == TargetInstrInfo::IMPLICIT_DEF)
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if (MI->getOpcode() == TargetInstrInfo::KILL)
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continue;
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continue;
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// Check if this instruction has a dependence on the critical path that
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// Check if this instruction has a dependence on the critical path that
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