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Extract some pointer hacking to a function. 

Switch to MCSuperRegIterator while we're there.

llvm-svn: 157717
This commit is contained in:
Jakob Stoklund Olesen 2012-05-30 22:40:03 +00:00
parent 68f6d3b1a6
commit 0b97dbcf1a
1 changed files with 22 additions and 22 deletions
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44
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
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@ -209,6 +209,16 @@ bool HexagonFrameLowering::hasFP(const MachineFunction &MF) const {
FuncInfo->hasClobberLR() ); FuncInfo->hasClobberLR() );
} }
static inline
unsigned uniqueSuperReg(unsigned Reg, const TargetRegisterInfo *TRI) {
MCSuperRegIterator SRI(Reg, TRI);
assert(SRI.isValid() && "Expected a superreg");
unsigned SuperReg = *SRI;
++SRI;
assert(!SRI.isValid() && "Expected exactly one superreg");
return SuperReg;
}
bool bool
HexagonFrameLowering::spillCalleeSavedRegisters( HexagonFrameLowering::spillCalleeSavedRegisters(
MachineBasicBlock &MBB, MachineBasicBlock &MBB,
@ -235,26 +245,21 @@ HexagonFrameLowering::spillCalleeSavedRegisters(
// //
// Check if we can use a double-word store. // Check if we can use a double-word store.
// //
const uint16_t* SuperReg = TRI->getSuperRegisters(Reg); unsigned SuperReg = uniqueSuperReg(Reg, TRI);
// Assume that there is exactly one superreg.
assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg");
bool CanUseDblStore = false; bool CanUseDblStore = false;
const TargetRegisterClass* SuperRegClass = 0; const TargetRegisterClass* SuperRegClass = 0;
if (ContiguousRegs && (i < CSI.size()-1)) { if (ContiguousRegs && (i < CSI.size()-1)) {
const uint16_t* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg()); unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI);
assert(SuperRegNext[0] && !SuperRegNext[1] && SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg);
"Expected exactly one superreg"); CanUseDblStore = (SuperRegNext == SuperReg);
SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]);
CanUseDblStore = (SuperRegNext[0] == SuperReg[0]);
} }
if (CanUseDblStore) { if (CanUseDblStore) {
TII.storeRegToStackSlot(MBB, MI, SuperReg[0], true, TII.storeRegToStackSlot(MBB, MI, SuperReg, true,
CSI[i+1].getFrameIdx(), SuperRegClass, TRI); CSI[i+1].getFrameIdx(), SuperRegClass, TRI);
MBB.addLiveIn(SuperReg[0]); MBB.addLiveIn(SuperReg);
++i; ++i;
} else { } else {
// Cannot use a double-word store. // Cannot use a double-word store.
@ -295,25 +300,20 @@ bool HexagonFrameLowering::restoreCalleeSavedRegisters(
// //
// Check if we can use a double-word load. // Check if we can use a double-word load.
// //
const uint16_t* SuperReg = TRI->getSuperRegisters(Reg); unsigned SuperReg = uniqueSuperReg(Reg, TRI);
const TargetRegisterClass* SuperRegClass = 0; const TargetRegisterClass* SuperRegClass = 0;
// Assume that there is exactly one superreg.
assert(SuperReg[0] && !SuperReg[1] && "Expected exactly one superreg");
bool CanUseDblLoad = false; bool CanUseDblLoad = false;
if (ContiguousRegs && (i < CSI.size()-1)) { if (ContiguousRegs && (i < CSI.size()-1)) {
const uint16_t* SuperRegNext = TRI->getSuperRegisters(CSI[i+1].getReg()); unsigned SuperRegNext = uniqueSuperReg(CSI[i+1].getReg(), TRI);
assert(SuperRegNext[0] && !SuperRegNext[1] && SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg);
"Expected exactly one superreg"); CanUseDblLoad = (SuperRegNext == SuperReg);
SuperRegClass = TRI->getMinimalPhysRegClass(SuperReg[0]);
CanUseDblLoad = (SuperRegNext[0] == SuperReg[0]);
} }
if (CanUseDblLoad) { if (CanUseDblLoad) {
TII.loadRegFromStackSlot(MBB, MI, SuperReg[0], CSI[i+1].getFrameIdx(), TII.loadRegFromStackSlot(MBB, MI, SuperReg, CSI[i+1].getFrameIdx(),
SuperRegClass, TRI); SuperRegClass, TRI);
MBB.addLiveIn(SuperReg[0]); MBB.addLiveIn(SuperReg);
++i; ++i;
} else { } else {
// Cannot use a double-word load. // Cannot use a double-word load.