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[AArch64] Enablement of Cortex-X2 

Enables support for Cortex-X2 cores.

Differential Revision: https://reviews.llvm.org/D112459
This commit is contained in:
Mubashar Ahmad 2021-11-01 11:55:24 +00:00 committed by David Green
parent 6fc50e531d
commit 0b83a18a2b
8 changed files with 46 additions and 4 deletions
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3
clang/docs/ReleaseNotes.rst
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@ -193,6 +193,8 @@ Arm and AArch64 Support in Clang
- Support has been added for the following processors (command-line identifiers in parentheses):
- Arm Cortex-A510 (``cortex-a510``)
- Arm Cortex-X2 (``cortex-x2``)
- The -mtune flag is no longer ignored for AArch64. It is now possible to
tune code generation for a particular CPU with -mtune without setting any
architectural features. For example, compiling with
@ -200,7 +202,6 @@ Arm and AArch64 Support in Clang
architecture features, but will enable certain optimizations specific to
Cortex-A57 CPUs and enable the use of a more accurate scheduling model.
Internal API Changes
--------------------

9
clang/test/Driver/aarch64-cpus.c
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@ -404,6 +404,15 @@
// RUN: %clang -target aarch64 -mcpu=cortex-a510+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A510-CRYPTO %s
// CORTEX-A510-CRYPTO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+sm4" "-target-feature" "+sha3" "-target-feature" "+sha2" "-target-feature" "+aes"
// RUN: %clang -target aarch64 -mcpu=cortex-x2 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-X2 %s
// CORTEX-X2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-x2"
// CORTEX-X2-NOT: "-target-feature" "{{[+-]}}sm4"
// CORTEX-X2-NOT: "-target-feature" "{{[+-]}}sha3"
// CORTEX-X2-NOT: "-target-feature" "{{[+-]}}aes"
// CORTEX-X2-SAME: {{$}}
// RUN: %clang -target aarch64 -mcpu=cortex-x2+crypto -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-X2-CRYPTO %s
// CORTEX-X2-CRYPTO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+sm4" "-target-feature" "+sha3" "-target-feature" "+sha2" "-target-feature" "+aes"
// RUN: %clang -target aarch64_be -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CA57-BE %s
// RUN: %clang -target aarch64 -mbig-endian -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CA57-BE %s
// RUN: %clang -target aarch64_be -mbig-endian -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CA57-BE %s

4
clang/test/Misc/target-invalid-cpu-note.c
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@ -5,11 +5,11 @@
// RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64
// AARCH64: error: unknown target CPU 'not-a-cpu'
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-r82, cortex-x1, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-m1, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel{{$}}
// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-r82, cortex-x1, cortex-x2, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-m1, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel{{$}}
// RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64
// TUNE_AARCH64: error: unknown target CPU 'not-a-cpu'
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-r82, cortex-x1, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-m1, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel{{$}}
// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-r82, cortex-x1, cortex-x2, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-m1, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel{{$}}
// RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86
// X86: error: unknown target CPU 'not-a-cpu'

4
llvm/include/llvm/Support/AArch64TargetParser.def
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@ -182,6 +182,10 @@ AARCH64_CPU_NAME("cortex-r82", ARMV8R, FK_CRYPTO_NEON_FP_ARMV8, false,
AARCH64_CPU_NAME("cortex-x1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
AArch64::AEK_SSBS))
AARCH64_CPU_NAME("cortex-x2", ARMV9A, FK_NEON_FP_ARMV8, false,
(AArch64::AEK_MTE | AArch64::AEK_BF16 | AArch64::AEK_I8MM |
AArch64::AEK_PAUTH | AArch64::AEK_SSBS | AArch64::AEK_SVE2BITPERM |
AArch64::AEK_SB | AArch64::AEK_FP16FML))
AARCH64_CPU_NAME("neoverse-e1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
(AArch64::AEK_DOTPROD | AArch64::AEK_FP16 | AArch64::AEK_RAS |
AArch64::AEK_RCPC | AArch64::AEK_SSBS))

12
llvm/lib/Target/AArch64/AArch64.td
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@ -691,6 +691,12 @@ def TuneX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
FeatureFuseAES,
FeaturePostRAScheduler]>;
def TuneX2 : SubtargetFeature<"cortex-x2", "ARMProcFamily", "CortexX2",
"Cortex-X2 ARM processors", [
FeatureFuseAES,
FeaturePostRAScheduler,
FeatureCmpBccFusion]>;
def TuneA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
"Fujitsu A64FX processors", [
FeaturePostRAScheduler,
@ -941,6 +947,10 @@ def ProcessorFeatures {
list<SubtargetFeature> X1 = [HasV8_2aOps, FeatureCrypto, FeatureFPARMv8,
FeatureNEON, FeatureRCPC, FeaturePerfMon,
FeatureSPE, FeatureFullFP16, FeatureDotProd];
list<SubtargetFeature> X2 = [HasV9_0aOps, FeatureNEON, FeaturePerfMon,
FeatureMatMulInt8, FeatureBF16, FeatureAM,
FeatureMTE, FeatureETE, FeatureSVE2BitPerm,
FeatureFP16FML];
list<SubtargetFeature> A64FX = [HasV8_2aOps, FeatureFPARMv8, FeatureNEON,
FeatureSHA2, FeaturePerfMon, FeatureFullFP16,
FeatureSVE, FeatureComplxNum];
@ -1049,6 +1059,8 @@ def : ProcessorModel<"cortex-r82", CortexA55Model, ProcessorFeatures.R82,
[TuneR82]>;
def : ProcessorModel<"cortex-x1", CortexA57Model, ProcessorFeatures.X1,
[TuneX1]>;
def : ProcessorModel<"cortex-x2", CortexA57Model, ProcessorFeatures.X2,
[TuneX2]>;
def : ProcessorModel<"neoverse-e1", CortexA53Model,
ProcessorFeatures.NeoverseE1, [TuneNeoverseE1]>;
def : ProcessorModel<"neoverse-n1", CortexA57Model,

4
llvm/lib/Target/AArch64/AArch64Subtarget.cpp
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@ -104,6 +104,10 @@ void AArch64Subtarget::initializeProperties() {
case CortexX1:
PrefFunctionLogAlignment = 4;
break;
case CortexX2:
PrefFunctionLogAlignment = 4;
VScaleForTuning = 1;
break;
case A64FX:
CacheLineSize = 256;
PrefFunctionLogAlignment = 3;

1
llvm/lib/Target/AArch64/AArch64Subtarget.h
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@ -62,6 +62,7 @@ public:
CortexA78C,
CortexR82,
CortexX1,
CortexX2,
ExynosM3,
Falkor,
Kryo,

13
llvm/unittests/Support/TargetParserTest.cpp
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@ -1008,6 +1008,17 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
AArch64::AEK_SSBS,
"8.2-A"),
ARMCPUTestParams("cortex-x2", "armv9-a", "neon-fp-armv8",
AArch64::AEK_CRC | AArch64::AEK_FP |
AArch64::AEK_SIMD | AArch64::AEK_RAS |
AArch64::AEK_LSE | AArch64::AEK_RDM |
AArch64::AEK_RCPC | AArch64::AEK_SVE2 |
AArch64::AEK_DOTPROD | AArch64::AEK_MTE |
AArch64::AEK_PAUTH | AArch64::AEK_I8MM |
AArch64::AEK_BF16 | AArch64::AEK_SVE2BITPERM |
AArch64::AEK_SSBS | AArch64::AEK_SB |
AArch64::AEK_FP16FML,
"9-A"),
ARMCPUTestParams("cyclone", "armv8-a", "crypto-neon-fp-armv8",
AArch64::AEK_NONE | AArch64::AEK_CRYPTO |
AArch64::AEK_FP | AArch64::AEK_SIMD,
@ -1197,7 +1208,7 @@ INSTANTIATE_TEST_SUITE_P(
AArch64::AEK_LSE | AArch64::AEK_RDM,
"8.2-A")));
static constexpr unsigned NumAArch64CPUArchs = 50;
static constexpr unsigned NumAArch64CPUArchs = 51;
TEST(TargetParserTest, testAArch64CPUArchList) {
SmallVector<StringRef, NumAArch64CPUArchs> List;