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[ARM] Fix unwind information for floating point registers 

Fixes the unwind information generated for floating-point registers.
Previously, all padding registers were assumed to be four bytes wide. Now, the
width of the register is used to specify the amount of padding.

Patch by Jackson Woodruff!

Differential revision: https://reviews.llvm.org/D51494

llvm-svn: 342545
This commit is contained in:
Oliver Stannard 2018-09-19 13:25:31 +00:00
parent 875c938fec
commit 0b835be7bb
2 changed files with 22 additions and 3 deletions
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10
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -1071,10 +1071,12 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
const MachineFunction &MF = *MI->getParent()->getParent();
const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
const TargetRegisterInfo *TargetRegInfo =
MF.getSubtarget().getRegisterInfo();
const MachineRegisterInfo &MachineRegInfo = MF.getRegInfo();
const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
unsigned FramePtr = RegInfo->getFrameRegister(MF);
unsigned FramePtr = TargetRegInfo->getFrameRegister(MF);
unsigned Opc = MI->getOpcode();
unsigned SrcReg, DstReg;
@ -1131,7 +1133,9 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
if (MO.isUndef()) {
assert(RegList.empty() &&
"Pad registers must come before restored ones");
Pad += 4;
unsigned Width =
TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
Pad += Width;
continue;
}
RegList.push_back(MO.getReg());

15
llvm/test/CodeGen/ARM/unwind-fp.ll Normal file
View File

@ -0,0 +1,15 @@
; RUN: llc < %s -mtriple=armv7a-arm-none-eabi | FileCheck %s
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "armv7-arm-none-eabi"
define void @foo() minsize {
entry:
; CHECK: .vsave {[[SAVE_REG:d[0-9]+]]}
; CHECK-NEXT: .pad #8
; CHECK-NEXT: vpush {[[PAD_REG:d[0-9]+]], [[SAVE_REG]]}
; CHECK: vpop {[[PAD_REG]], [[SAVE_REG]]}
%a = alloca i32, align 4
call void asm sideeffect "", "r,~{d8}"(i32* %a)
ret void
}