forked from OSchip/llvm-project
[LLD][ELF][ARM] Do not substitute BL/BLX for non STT_FUNC symbols.
D73474 disabled the generation of interworking thunks for branch relocations to non STT_FUNC symbols. This patch handles the case of BL and BLX instructions to non STT_FUNC symbols. LLD would normally look at the state of the caller and the callee and write a BL if the states are the same and a BLX if the states are different. This patch disables BL/BLX substitution when the destination symbol does not have type STT_FUNC. This brings our behavior in line with GNU ld which may prevent difficult to diagnose runtime errors when switching to lld. Differential Revision: https://reviews.llvm.org/D73542
This commit is contained in:
Peter Smith
parent
63c8972562
commit
0b4a047bfb
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@ -402,11 +402,15 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
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checkInt(loc, val, 31, rel);
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write32le(loc, (read32le(loc) & 0x80000000) | (val & ~0x80000000));
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break;
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case R_ARM_CALL:
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// R_ARM_CALL is used for BL and BLX instructions, depending on the
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// value of bit 0 of Val, we must select a BL or BLX instruction
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if (val & 1) {
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// If bit 0 of Val is 1 the target is Thumb, we must select a BLX.
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case R_ARM_CALL: {
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// R_ARM_CALL is used for BL and BLX instructions, for symbols of type
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// STT_FUNC we choose whether to write a BL or BLX depending on the
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// value of bit 0 of Val. With bit 0 == 1 denoting Thumb. If the symbol is
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// not of type STT_FUNC then we must preserve the original instruction.
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// PLT entries are always ARM state so we know we don't need to interwork.
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bool isBlx = (read32le(loc) & 0xfe000000) == 0xfa000000;
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bool interwork = rel.sym && rel.sym->isFunc() && rel.type != R_PLT_PC;
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if (interwork ? val & 1 : isBlx) {
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// The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
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checkInt(loc, val, 26, rel);
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write32le(loc, 0xfa000000 | // opcode
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@ -414,11 +418,11 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
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((val >> 2) & 0x00ffffff)); // imm24
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break;
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}
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if ((read32le(loc) & 0xfe000000) == 0xfa000000)
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// BLX (always unconditional) instruction to an ARM Target, select an
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// unconditional BL.
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write32le(loc, 0xeb000000 | (read32le(loc) & 0x00ffffff));
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// BLX (always unconditional) instruction to an ARM Target, select an
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// unconditional BL.
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write32le(loc, 0xeb000000 | (read32le(loc) & 0x00ffffff));
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// fall through as BL encoding is shared with B
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}
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LLVM_FALLTHROUGH;
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case R_ARM_JUMP24:
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case R_ARM_PC24:
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@ -443,16 +447,23 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
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((val >> 5) & 0x2000) | // J1
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((val >> 1) & 0x07ff)); // imm11
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break;
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case R_ARM_THM_CALL:
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// R_ARM_THM_CALL is used for BL and BLX instructions, depending on the
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// value of bit 0 of Val, we must select a BL or BLX instruction
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if ((val & 1) == 0) {
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// Ensure BLX destination is 4-byte aligned. As BLX instruction may
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// only be two byte aligned. This must be done before overflow check
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case R_ARM_THM_CALL: {
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// R_ARM_THM_CALL is used for BL and BLX instructions, for symbols of type
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// STT_FUNC we choose whether to write a BL or BLX depending on the
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// value of bit 0 of Val. With bit 0 == 0 denoting ARM, if the symbol is
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// not of type STT_FUNC then we must preserve the original instruction.
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// PLT entries are always ARM state so we know we need to interwork.
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bool isBlx = (read16le(loc + 2) & 0x1000) == 0;
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bool interwork = (rel.sym && rel.sym->isFunc()) || rel.type == R_PLT_PC;
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if (interwork ? (val & 1) == 0 : isBlx) {
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// We are writing a BLX. Ensure BLX destination is 4-byte aligned. As
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// the BLX instruction may only be two byte aligned. This must be done
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// before overflow check.
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val = alignTo(val, 4);
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write16le(loc + 2, read16le(loc + 2) & ~0x1000);
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} else {
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write16le(loc + 2, (read16le(loc + 2) & ~0x1000) | 1 << 12);
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}
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// Bit 12 is 0 for BLX, 1 for BL
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write16le(loc + 2, (read16le(loc + 2) & ~0x1000) | (val & 1) << 12);
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if (!config->armJ1J2BranchEncoding) {
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// Older Arm architectures do not support R_ARM_THM_JUMP24 and have
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// different encoding rules and range due to J1 and J2 always being 1.
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@ -466,6 +477,7 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
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((val >> 1) & 0x07ff)); // imm11
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break;
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}
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}
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// Fall through as rest of encoding is the same as B.W
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LLVM_FALLTHROUGH;
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case R_ARM_THM_JUMP24:
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@ -23,7 +23,9 @@ thumb_func_with_explicit_notype:
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/// All the symbols that are targets of the branch relocations do not have
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/// type STT_FUNC. LLD should not insert interworking thunks as non STT_FUNC
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/// symbols have no state information, the ABI assumes the user has manually
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/// done the interworking.
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/// done the interworking. For the BL and BLX instructions LLD should
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/// preserve the original instruction instead of writing out the correct one
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/// for the assumed state at the target.
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.section .arm_caller, "ax", %progbits
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.balign 4
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.arm
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@ -35,10 +37,24 @@ _start:
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b .thumb_target
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b thumb_func_with_notype
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b thumb_func_with_explicit_notype
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bl .arm_target
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bl arm_func_with_notype
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bl arm_func_with_explicit_notype
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bl .thumb_target
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bl thumb_func_with_notype
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bl thumb_func_with_explicit_notype
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blx .arm_target
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blx arm_func_with_notype
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blx arm_func_with_explicit_notype
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blx .thumb_target
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blx thumb_func_with_notype
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blx thumb_func_with_explicit_notype
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.section .thumb_caller, "ax", %progbits
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.thumb
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.balign 4
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.global thumb_caller
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thumb_caller:
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b.w .arm_target
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b.w arm_func_with_notype
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b.w arm_func_with_explicit_notype
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@ -51,6 +67,18 @@ _start:
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beq.w .thumb_target
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beq.w thumb_func_with_notype
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beq.w thumb_func_with_explicit_notype
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bl .arm_target
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bl arm_func_with_notype
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bl arm_func_with_explicit_notype
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bl .thumb_target
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bl thumb_func_with_notype
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bl thumb_func_with_explicit_notype
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blx .arm_target
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blx arm_func_with_notype
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blx arm_func_with_explicit_notype
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blx .thumb_target
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blx thumb_func_with_notype
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blx thumb_func_with_explicit_notype
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// CHECK: 00012008 _start:
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// CHECK-NEXT: 12008: b #-16
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@ -59,15 +87,41 @@ _start:
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// CHECK-NEXT: 12014: b #-24
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// CHECK-NEXT: 12018: b #-28
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// CHECK-NEXT: 1201c: b #-32
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// CHECK: 12020: b.w #-36
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// CHECK-NEXT: 12024: b.w #-40
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// CHECK-NEXT: 12028: b.w #-44
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// CHECK-NEXT: 1202c: b.w #-44
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// CHECK-NEXT: 12030: b.w #-48
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// CHECK-NEXT: 12034: b.w #-52
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// CHECK-NEXT: 12038: beq.w #-60
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// CHECK-NEXT: 1203c: beq.w #-64
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// CHECK-NEXT: 12040: beq.w #-68
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// CHECK-NEXT: 12044: beq.w #-68
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// CHECK-NEXT: 12048: beq.w #-72
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// CHECK-NEXT: 1204c: beq.w #-76
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// CHECK-NEXT: 12020: bl #-40
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// CHECK-NEXT: 12024: bl #-44
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// CHECK-NEXT: 12028: bl #-48
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// CHECK-NEXT: 1202c: bl #-48
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// CHECK-NEXT: 12030: bl #-52
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// CHECK-NEXT: 12034: bl #-56
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// CHECK-NEXT: 12038: blx #-64
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// CHECK-NEXT: 1203c: blx #-68
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// CHECK-NEXT: 12040: blx #-72
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// CHECK-NEXT: 12044: blx #-72
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// CHECK-NEXT: 12048: blx #-76
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// CHECK-NEXT: 1204c: blx #-80
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// CHECK: 00012050 thumb_caller:
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// CHECK-NEXT: 12050: b.w #-84
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// CHECK-NEXT: 12054: b.w #-88
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// CHECK-NEXT: 12058: b.w #-92
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// CHECK-NEXT: 1205c: b.w #-92
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// CHECK-NEXT: 12060: b.w #-96
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// CHECK-NEXT: 12064: b.w #-100
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// CHECK-NEXT: 12068: beq.w #-108
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// CHECK-NEXT: 1206c: beq.w #-112
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// CHECK-NEXT: 12070: beq.w #-116
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// CHECK-NEXT: 12074: beq.w #-116
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// CHECK-NEXT: 12078: beq.w #-120
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// CHECK-NEXT: 1207c: beq.w #-124
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// CHECK-NEXT: 12080: bl #-132
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// CHECK-NEXT: 12084: bl #-136
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// CHECK-NEXT: 12088: bl #-140
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// CHECK-NEXT: 1208c: bl #-140
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// CHECK-NEXT: 12090: bl #-144
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// CHECK-NEXT: 12094: bl #-148
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// CHECK-NEXT: 12098: blx #-156
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// CHECK-NEXT: 1209c: blx #-160
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// CHECK-NEXT: 120a0: blx #-164
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// CHECK-NEXT: 120a4: blx #-164
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// CHECK-NEXT: 120a8: blx #-168
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// CHECK-NEXT: 120ac: blx #-172
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@ -10,6 +10,7 @@
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.syntax unified
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.weak target
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.type target, %function
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.text
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.global _start
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@ -12,6 +12,7 @@
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.syntax unified
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.weak target
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.type target, %function
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.text
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.global _start
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