forked from OSchip/llvm-project
[Support] Ensure KnownBits::sextInReg can handle the src == dst sext-in-reg case.
This was resulting in assertions inside APInt::zext that we were extending to the same bitwidth.
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@ -85,7 +85,11 @@ KnownBits KnownBits::computeForAddSub(bool Add, bool NSW,
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KnownBits KnownBits::sextInReg(unsigned SrcBitWidth) const {
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unsigned BitWidth = getBitWidth();
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assert(BitWidth >= SrcBitWidth && "Illegal sext-in-register");
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assert(0 < SrcBitWidth && SrcBitWidth <= BitWidth &&
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"Illegal sext-in-register");
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if (SrcBitWidth == BitWidth)
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return *this;
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// Sign extension. Compute the demanded bits in the result that are not
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// present in the input.
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@ -427,7 +427,7 @@ TEST(KnownBitsTest, SExtOrTrunc) {
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TEST(KnownBitsTest, SExtInReg) {
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unsigned Bits = 4;
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for (unsigned FromBits = 1; FromBits != Bits; ++FromBits) {
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for (unsigned FromBits = 1; FromBits <= Bits; ++FromBits) {
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ForeachKnownBits(Bits, [&](const KnownBits &Known) {
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APInt CommonOne = APInt::getAllOnesValue(Bits);
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APInt CommonZero = APInt::getAllOnesValue(Bits);
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