forked from OSchip/llvm-project
[Hexagon] Do not move a block if it is on a fall-through path
llvm-svn: 301698
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@ -38,6 +38,7 @@ class HexagonCFGOptimizer : public MachineFunctionPass {
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private:
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void InvertAndChangeJumpTarget(MachineInstr &, MachineBasicBlock *);
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bool isOnFallThroughPath(MachineBasicBlock *MBB);
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public:
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static char ID;
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@ -106,6 +107,14 @@ void HexagonCFGOptimizer::InvertAndChangeJumpTarget(
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MI.getOperand(1).setMBB(NewTarget);
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}
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bool HexagonCFGOptimizer::isOnFallThroughPath(MachineBasicBlock *MBB) {
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if (MBB->canFallThrough())
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return true;
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for (MachineBasicBlock *PB : MBB->predecessors())
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if (PB->isLayoutSuccessor(MBB) && PB->canFallThrough())
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return true;
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return false;
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}
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bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
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if (skipFunction(*Fn.getFunction()))
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@ -182,7 +191,6 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
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}
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if ((NumSuccs == 2) && LayoutSucc && (LayoutSucc->pred_size() == 1)) {
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// Ensure that BB2 has one instruction -- an unconditional jump.
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if ((LayoutSucc->size() == 1) &&
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IsUnconditionalJump(LayoutSucc->front().getOpcode())) {
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@ -211,9 +219,8 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) {
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JumpAroundTarget->moveAfter(LayoutSucc);
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// only move a block if it doesn't have a fall-thru. otherwise
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// the CFG will be incorrect.
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if (!UncondTarget->canFallThrough()) {
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if (!isOnFallThroughPath(UncondTarget))
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UncondTarget->moveAfter(JumpAroundTarget);
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}
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}
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//
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@ -0,0 +1,71 @@
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; RUN: llc -march=hexagon -verify-machineinstrs < %s | FileCheck %s
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; REQUIRES: asserts
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; Check for some sane output. This test used to crash.
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; CHECK: jumpr r31
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define i32 @fred(i32 %a0, i8 zeroext %a1) local_unnamed_addr #0 {
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b2:
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br i1 undef, label %b4, label %b3
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b3: ; preds = %b2
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unreachable
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b4: ; preds = %b2
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br i1 undef, label %b19, label %b5
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b5: ; preds = %b4
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br i1 undef, label %b6, label %b12
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b6: ; preds = %b5
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switch i8 %a1, label %b17 [
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i8 2, label %b7
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i8 5, label %b7
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i8 1, label %b7
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i8 3, label %b8
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]
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b7: ; preds = %b6, %b6, %b6
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unreachable
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b8: ; preds = %b6
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br i1 undef, label %b11, label %b9
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b9: ; preds = %b8
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%v10 = or i32 undef, 0
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br label %b15
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b11: ; preds = %b8
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unreachable
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b12: ; preds = %b5
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switch i8 %a1, label %b17 [
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i8 5, label %b13
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i8 1, label %b13
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i8 2, label %b14
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i8 3, label %b15
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]
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b13: ; preds = %b12, %b12
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store i32 %a0, i32* undef, align 4
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br label %b17
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b14: ; preds = %b12
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store i16 undef, i16* undef, align 4
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br label %b17
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b15: ; preds = %b12, %b9
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%v16 = phi i32 [ 0, %b12 ], [ %v10, %b9 ]
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store i32 undef, i32* undef, align 4
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br label %b17
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b17: ; preds = %b15, %b14, %b13, %b12, %b6
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%v18 = phi i32 [ 0, %b13 ], [ 0, %b12 ], [ %v16, %b15 ], [ 0, %b14 ], [ 0, %b6 ]
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ret i32 %v18
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b19: ; preds = %b4
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unreachable
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" }
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