forked from OSchip/llvm-project
Refactor the LowerVectorTransfers pass to use the RewritePattern infra - NFC
This is step 1/n in refactoring infrastructure along the Vector dialect to make it ready for retargetability and composable progressive lowering. PiperOrigin-RevId: 280529784
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@ -1,4 +1,4 @@
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//===- VectorToLLVM.h - Pass converting vector to LLVM dialect --*- C++ -*-===//
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//===- VectorConversions.h - Utils to convert from the vector dialect -----===//
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//
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// Copyright 2019 The MLIR Authors.
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//
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@ -19,10 +19,17 @@
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namespace mlir {
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class LLVMTypeConverter;
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class MLIRContext;
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class ModuleOp;
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template <typename T> class OpPassBase;
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class OwningRewritePatternList;
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template <typename T> class OpPassBase;
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/// Collect a set of patterns to convert from the Vector dialect to affine loops
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/// surrounding ops in different dialects (vector, std etc).
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/// This is the general place where we want to implement Vector -> Vector and
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/// Vector -> Std legalizations.
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void populateVectorToAffineLoopsConversionPatterns(
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MLIRContext *context, OwningRewritePatternList &patterns);
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/// Collect a set of patterns to convert from the Vector dialect to LLVM.
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void populateVectorToLLVMConversionPatterns(LLVMTypeConverter &converter,
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@ -30,6 +37,7 @@ void populateVectorToLLVMConversionPatterns(LLVMTypeConverter &converter,
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/// Create a pass to convert vector operations to the LLVMIR dialect.
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OpPassBase<ModuleOp> *createLowerVectorToLLVMPass();
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} // namespace mlir
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#endif // MLIR_CONVERSION_VECTORTOLLVM_VECTORTOLLVM_H_
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@ -122,9 +122,6 @@ std::unique_ptr<OpPassBase<FuncOp>> createAffineDataCopyGenerationPass(
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unsigned tagMemorySpace = 0, int minDmaTransferSize = 1024,
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uint64_t fastMemCapacityBytes = std::numeric_limits<uint64_t>::max());
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/// Creates a pass to lower VectorTransferReadOp and VectorTransferWriteOp.
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std::unique_ptr<OpPassBase<FuncOp>> createLowerVectorTransfersPass();
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/// Creates a pass to perform optimizations relying on memref dataflow such as
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/// store to load forwarding, elimination of dead stores, and dead allocs.
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std::unique_ptr<OpPassBase<FuncOp>> createMemRefDataFlowOptPass();
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@ -7,4 +7,4 @@ add_subdirectory(LoopsToGPU)
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add_subdirectory(LoopToStandard)
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add_subdirectory(StandardToLLVM)
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add_subdirectory(StandardToSPIRV)
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add_subdirectory(VectorToLLVM)
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add_subdirectory(VectorConversions)
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@ -1,8 +1,9 @@
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add_llvm_library(MLIRVectorToLLVM
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VectorToLLVM.cpp
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VectorToLoops.cpp
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ADDITIONAL_HEADER_DIRS
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${MLIR_MAIN_INCLUDE_DIR}/mlir/Conversion/VectorToLLVM
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${MLIR_MAIN_INCLUDE_DIR}/mlir/Conversion/VectorConversions
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)
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set(LIBS
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MLIRLLVMIR
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@ -1,4 +1,4 @@
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//===- LowerToLLVMDialect.cpp - conversion from Linalg to LLVM dialect ----===//
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//===- VectorToLLVM.cpp - Conversion from Vector to the LLVM dialect ------===//
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//
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// Copyright 2019 The MLIR Authors.
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//
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@ -15,7 +15,7 @@
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// limitations under the License.
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// =============================================================================
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#include "mlir/Conversion/VectorToLLVM/VectorToLLVM.h"
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#include "mlir/Conversion/VectorConversions/VectorConversions.h"
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#include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
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#include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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@ -1,4 +1,4 @@
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//===- LowerVectorTransfers.cpp - LowerVectorTransfers Pass Impl ----------===//
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//===- VectorToLoops.cpp - Conversion from Vector to mix of Loops and Std -===//
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//
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// Copyright 2019 The MLIR Authors.
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//
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@ -21,12 +21,7 @@
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#include <type_traits>
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#include "mlir/Analysis/AffineAnalysis.h"
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#include "mlir/Analysis/NestedMatcher.h"
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#include "mlir/Analysis/Utils.h"
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#include "mlir/Analysis/VectorAnalysis.h"
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#include "mlir/Dialect/LoopOps/LoopOps.h"
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#include "mlir/Dialect/StandardOps/Ops.h"
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#include "mlir/Conversion/VectorConversions/VectorConversions.h"
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#include "mlir/Dialect/VectorOps/VectorOps.h"
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#include "mlir/EDSC/Builders.h"
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#include "mlir/EDSC/Helpers.h"
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@ -39,9 +34,12 @@
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#include "mlir/IR/OperationSupport.h"
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#include "mlir/IR/PatternMatch.h"
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#include "mlir/IR/Types.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Support/Functional.h"
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#include "mlir/Transforms/Passes.h"
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using namespace mlir;
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using vector::VectorTransferReadOp;
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using vector::VectorTransferWriteOp;
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namespace {
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/// Implements lowering of VectorTransferReadOp and VectorTransferWriteOp to a
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/// proper abstraction for the hardware.
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@ -58,7 +56,7 @@
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/// loop.for %i0 = 0 to %0 {
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/// loop.for %i1 = 0 to %1 step %c256 {
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/// loop.for %i2 = 0 to %2 step %c32 {
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/// %v = vector.transfer_read %A[%i0, %i1, %i2], (%f0)
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/// %v = vector.transfer_read %A[%i0, %i1, %i2], %f0
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/// {permutation_map: (d0, d1, d2) -> (d2, d1)} :
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/// memref<?x?x?xf32>, vector<32x256xf32>
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/// }}}
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@ -81,17 +79,16 @@
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/// which creates individual indexing expressions of the form:
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///
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/// ```mlir-dsc
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/// SELECT(i + ii < zero, zero, SELECT(i + ii < N, i + ii, N - one))
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/// auto condMax = i + ii < N;
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/// auto max = select(condMax, i + ii, N - one)
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/// auto cond = i + ii < zero;
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/// select(cond, zero, max);
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/// ```
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using namespace mlir;
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using vector::VectorTransferReadOp;
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using vector::VectorTransferWriteOp;
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#define DEBUG_TYPE "affine-lower-vector-transfers"
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namespace {
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///
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/// In the future, clipping should not be the only way and instead we should
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/// load vectors + mask them. Similarly on the write side, load/mask/store for
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/// implementing RMW behavior.
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///
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/// Lowers VectorTransferOp into a combination of:
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/// 1. local memory allocation;
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/// 2. perfect loop nest over:
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@ -359,26 +356,12 @@ VectorTransferRewriter<VectorTransferWriteOp>::matchAndRewrite(
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rewriter.eraseOp(op);
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return matchSuccess();
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}
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} // namespace
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struct LowerVectorTransfersPass
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: public FunctionPass<LowerVectorTransfersPass> {
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void runOnFunction() override {
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OwningRewritePatternList patterns;
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auto *context = &getContext();
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patterns.insert<VectorTransferRewriter<vector::VectorTransferReadOp>,
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VectorTransferRewriter<vector::VectorTransferWriteOp>>(
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context);
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applyPatternsGreedily(getFunction(), patterns);
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}
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};
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} // end anonymous namespace
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std::unique_ptr<OpPassBase<FuncOp>> mlir::createLowerVectorTransfersPass() {
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return std::make_unique<LowerVectorTransfersPass>();
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/// Populate the given list with patterns that convert from Vector to LLVM.
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void mlir::populateVectorToAffineLoopsConversionPatterns(
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MLIRContext *context, OwningRewritePatternList &patterns) {
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patterns.insert<VectorTransferRewriter<vector::VectorTransferReadOp>,
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VectorTransferRewriter<vector::VectorTransferWriteOp>>(
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context);
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}
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static PassRegistration<LowerVectorTransfersPass>
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pass("affine-lower-vector-transfers",
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"Materializes vector transfer ops to a "
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"proper abstraction for the hardware");
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@ -19,7 +19,7 @@
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#include "mlir/Conversion/LoopToStandard/ConvertLoopToStandard.h"
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#include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
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#include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
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#include "mlir/Conversion/VectorToLLVM/VectorToLLVM.h"
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#include "mlir/Conversion/VectorConversions/VectorConversions.h"
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#include "mlir/Dialect/LLVMIR/LLVMDialect.h"
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#include "mlir/Dialect/Linalg/IR/LinalgOps.h"
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#include "mlir/Dialect/Linalg/IR/LinalgTypes.h"
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@ -13,7 +13,6 @@ add_llvm_library(MLIRTransforms
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LoopTiling.cpp
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LoopUnrollAndJam.cpp
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LoopUnroll.cpp
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LowerVectorTransfers.cpp
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MaterializeVectors.cpp
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MemRefDataFlowOpt.cpp
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PipelineDataTransfer.cpp
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// RUN: mlir-opt %s -affine-lower-vector-transfers | FileCheck %s
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// RUN: mlir-opt %s -test-affine-lower-vector-transfers | FileCheck %s
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// CHECK: #[[ADD:map[0-9]+]] = (d0, d1) -> (d0 + d1)
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// CHECK: #[[SUB:map[0-9]+]] = ()[s0] -> (s0 - 1)
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@ -5,6 +5,7 @@ add_llvm_library(MLIRTestTransforms
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TestInlining.cpp
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TestLoopMapping.cpp
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TestLoopParametricTiling.cpp
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TestLowerVectorTransfers.cpp
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TestOpaqueLoc.cpp
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TestMemRefStrideCalculation.cpp
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TestVectorizationUtils.cpp
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@ -0,0 +1,44 @@
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//===- TestLowerVectorTransfers.cpp - Test VectorTransfers lowering -------===//
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//
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// Copyright 2019 The MLIR Authors.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// =============================================================================
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#include <type_traits>
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#include "mlir/Conversion/VectorConversions/VectorConversions.h"
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#include "mlir/IR/PatternMatch.h"
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#include "mlir/Pass/Pass.h"
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#include "mlir/Transforms/Passes.h"
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using namespace mlir;
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namespace {
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struct TestLowerVectorTransfersPass
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: public FunctionPass<TestLowerVectorTransfersPass> {
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void runOnFunction() override {
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OwningRewritePatternList patterns;
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auto *context = &getContext();
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populateVectorToAffineLoopsConversionPatterns(context, patterns);
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applyPatternsGreedily(getFunction(), patterns);
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}
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};
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} // end anonymous namespace
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static PassRegistration<TestLowerVectorTransfersPass>
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pass("test-affine-lower-vector-transfers",
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"Materializes vector transfer ops to a "
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"proper abstraction for the hardware");
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