forked from OSchip/llvm-project
[LoopVectorize][X86] Regenerate conversion-cost.ll tests
This commit is contained in:
Simon Pilgrim
parent
5e5ba14b4d
commit
0af9b25aff
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@ -1,12 +1,90 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -loop-vectorize -mtriple=x86_64-apple-macosx10.8.0 -mcpu=corei7-avx -S | FileCheck %s
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-apple-macosx10.8.0"
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;CHECK-LABEL: @conversion_cost1(
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;CHECK: store <32 x i8>
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;CHECK: ret
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define i32 @conversion_cost1(i32 %n, i8* nocapture %A, float* nocapture %B) nounwind uwtable ssp {
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; CHECK-LABEL: @conversion_cost1(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[N:%.*]], 3
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; CHECK-NEXT: br i1 [[TMP1]], label [[DOTLR_PH_PREHEADER:%.*]], label [[DOT_CRIT_EDGE:%.*]]
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; CHECK: .lr.ph.preheader:
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; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[N]], -4
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 32
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP4]], 32
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP4]], [[N_MOD_VF]]
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; CHECK-NEXT: [[IND_END:%.*]] = add i64 3, [[N_VEC]]
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <32 x i64> [ <i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15, i64 16, i64 17, i64 18, i64 19, i64 20, i64 21, i64 22, i64 23, i64 24, i64 25, i64 26, i64 27, i64 28, i64 29, i64 30, i64 31, i64 32, i64 33, i64 34>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND1:%.*]] = phi <32 x i8> [ <i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT2:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 3, [[INDEX]]
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; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
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; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 1
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; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 2
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; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 3
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; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 4
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; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 5
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; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 6
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; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 7
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; CHECK-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 8
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; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[OFFSET_IDX]], 9
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; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 10
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; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[OFFSET_IDX]], 11
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; CHECK-NEXT: [[TMP17:%.*]] = add i64 [[OFFSET_IDX]], 12
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; CHECK-NEXT: [[TMP18:%.*]] = add i64 [[OFFSET_IDX]], 13
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; CHECK-NEXT: [[TMP19:%.*]] = add i64 [[OFFSET_IDX]], 14
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; CHECK-NEXT: [[TMP20:%.*]] = add i64 [[OFFSET_IDX]], 15
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; CHECK-NEXT: [[TMP21:%.*]] = add i64 [[OFFSET_IDX]], 16
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; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[OFFSET_IDX]], 17
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; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[OFFSET_IDX]], 18
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; CHECK-NEXT: [[TMP24:%.*]] = add i64 [[OFFSET_IDX]], 19
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; CHECK-NEXT: [[TMP25:%.*]] = add i64 [[OFFSET_IDX]], 20
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; CHECK-NEXT: [[TMP26:%.*]] = add i64 [[OFFSET_IDX]], 21
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; CHECK-NEXT: [[TMP27:%.*]] = add i64 [[OFFSET_IDX]], 22
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; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[OFFSET_IDX]], 23
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; CHECK-NEXT: [[TMP29:%.*]] = add i64 [[OFFSET_IDX]], 24
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; CHECK-NEXT: [[TMP30:%.*]] = add i64 [[OFFSET_IDX]], 25
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; CHECK-NEXT: [[TMP31:%.*]] = add i64 [[OFFSET_IDX]], 26
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; CHECK-NEXT: [[TMP32:%.*]] = add i64 [[OFFSET_IDX]], 27
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; CHECK-NEXT: [[TMP33:%.*]] = add i64 [[OFFSET_IDX]], 28
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; CHECK-NEXT: [[TMP34:%.*]] = add i64 [[OFFSET_IDX]], 29
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; CHECK-NEXT: [[TMP35:%.*]] = add i64 [[OFFSET_IDX]], 30
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; CHECK-NEXT: [[TMP36:%.*]] = add i64 [[OFFSET_IDX]], 31
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; CHECK-NEXT: [[TMP37:%.*]] = getelementptr inbounds i8, i8* [[A:%.*]], i64 [[TMP5]]
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; CHECK-NEXT: [[TMP38:%.*]] = getelementptr inbounds i8, i8* [[TMP37]], i32 0
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; CHECK-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to <32 x i8>*
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; CHECK-NEXT: store <32 x i8> [[VEC_IND1]], <32 x i8>* [[TMP39]], align 1
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <32 x i64> [[VEC_IND]], <i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32, i64 32>
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; CHECK-NEXT: [[VEC_IND_NEXT2]] = add <32 x i8> [[VEC_IND1]], <i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32, i8 32>
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; CHECK-NEXT: [[TMP40:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP40]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP4]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[DOT_CRIT_EDGE_LOOPEXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 3, [[DOTLR_PH_PREHEADER]] ]
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; CHECK-NEXT: br label [[DOTLR_PH:%.*]]
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; CHECK: .lr.ph:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[DOTLR_PH]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[TMP41:%.*]] = trunc i64 [[INDVARS_IV]] to i8
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; CHECK-NEXT: [[TMP42:%.*]] = getelementptr inbounds i8, i8* [[A]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: store i8 [[TMP41]], i8* [[TMP42]], align 1
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LFTR_WIDEIV]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[DOT_CRIT_EDGE_LOOPEXIT]], label [[DOTLR_PH]], !llvm.loop [[LOOP2:![0-9]+]]
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; CHECK: ._crit_edge.loopexit:
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; CHECK-NEXT: br label [[DOT_CRIT_EDGE]]
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; CHECK: ._crit_edge:
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; CHECK-NEXT: ret i32 undef
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;
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%1 = icmp sgt i32 %n, 3
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br i1 %1, label %.lr.ph, label %._crit_edge
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@ -24,10 +102,85 @@ define i32 @conversion_cost1(i32 %n, i8* nocapture %A, float* nocapture %B) noun
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ret i32 undef
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}
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;CHECK-LABEL: @conversion_cost2(
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;CHECK: <2 x float>
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;CHECK: ret
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define i32 @conversion_cost2(i32 %n, i8* nocapture %A, float* nocapture %B) nounwind uwtable ssp {
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; CHECK-LABEL: @conversion_cost2(
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; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[N:%.*]], 9
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; CHECK-NEXT: br i1 [[TMP1]], label [[DOTLR_PH_PREHEADER:%.*]], label [[DOT_CRIT_EDGE:%.*]]
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; CHECK: .lr.ph.preheader:
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; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[N]], -10
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; CHECK-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
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; CHECK-NEXT: [[TMP4:%.*]] = add nuw nsw i64 [[TMP3]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP4]], 8
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP4]], 8
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP4]], [[N_MOD_VF]]
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; CHECK-NEXT: [[IND_END:%.*]] = add i64 9, [[N_VEC]]
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ <i64 9, i64 10>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[STEP_ADD:%.*]] = add <2 x i64> [[VEC_IND]], <i64 2, i64 2>
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; CHECK-NEXT: [[STEP_ADD1:%.*]] = add <2 x i64> [[STEP_ADD]], <i64 2, i64 2>
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; CHECK-NEXT: [[STEP_ADD2:%.*]] = add <2 x i64> [[STEP_ADD1]], <i64 2, i64 2>
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 9, [[INDEX]]
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; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 0
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; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 1
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; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 2
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; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 3
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; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[OFFSET_IDX]], 4
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; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[OFFSET_IDX]], 5
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; CHECK-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 6
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; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 7
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; CHECK-NEXT: [[TMP13:%.*]] = add nsw <2 x i64> [[VEC_IND]], <i64 3, i64 3>
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; CHECK-NEXT: [[TMP14:%.*]] = add nsw <2 x i64> [[STEP_ADD]], <i64 3, i64 3>
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; CHECK-NEXT: [[TMP15:%.*]] = add nsw <2 x i64> [[STEP_ADD1]], <i64 3, i64 3>
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; CHECK-NEXT: [[TMP16:%.*]] = add nsw <2 x i64> [[STEP_ADD2]], <i64 3, i64 3>
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; CHECK-NEXT: [[TMP17:%.*]] = sitofp <2 x i64> [[TMP13]] to <2 x float>
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; CHECK-NEXT: [[TMP18:%.*]] = sitofp <2 x i64> [[TMP14]] to <2 x float>
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; CHECK-NEXT: [[TMP19:%.*]] = sitofp <2 x i64> [[TMP15]] to <2 x float>
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; CHECK-NEXT: [[TMP20:%.*]] = sitofp <2 x i64> [[TMP16]] to <2 x float>
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; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds float, float* [[B:%.*]], i64 [[TMP5]]
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; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[TMP7]]
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; CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[TMP9]]
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; CHECK-NEXT: [[TMP24:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[TMP11]]
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; CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 0
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; CHECK-NEXT: [[TMP26:%.*]] = bitcast float* [[TMP25]] to <2 x float>*
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; CHECK-NEXT: store <2 x float> [[TMP17]], <2 x float>* [[TMP26]], align 4
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; CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 2
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; CHECK-NEXT: [[TMP28:%.*]] = bitcast float* [[TMP27]] to <2 x float>*
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; CHECK-NEXT: store <2 x float> [[TMP18]], <2 x float>* [[TMP28]], align 4
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; CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 4
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; CHECK-NEXT: [[TMP30:%.*]] = bitcast float* [[TMP29]] to <2 x float>*
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; CHECK-NEXT: store <2 x float> [[TMP19]], <2 x float>* [[TMP30]], align 4
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; CHECK-NEXT: [[TMP31:%.*]] = getelementptr inbounds float, float* [[TMP21]], i32 6
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; CHECK-NEXT: [[TMP32:%.*]] = bitcast float* [[TMP31]] to <2 x float>*
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; CHECK-NEXT: store <2 x float> [[TMP20]], <2 x float>* [[TMP32]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i64> [[STEP_ADD2]], <i64 2, i64 2>
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; CHECK-NEXT: [[TMP33:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP33]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP4]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label [[DOT_CRIT_EDGE_LOOPEXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 9, [[DOTLR_PH_PREHEADER]] ]
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; CHECK-NEXT: br label [[DOTLR_PH:%.*]]
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; CHECK: .lr.ph:
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; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[INDVARS_IV_NEXT:%.*]], [[DOTLR_PH]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[INDVARS_IV]], 3
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; CHECK-NEXT: [[TOFP:%.*]] = sitofp i64 [[ADD]] to float
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; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[INDVARS_IV]]
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; CHECK-NEXT: store float [[TOFP]], float* [[GEP]], align 4
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; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1
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; CHECK-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32
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; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i32 [[LFTR_WIDEIV]], [[N]]
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; CHECK-NEXT: br i1 [[EXITCOND]], label [[DOT_CRIT_EDGE_LOOPEXIT]], label [[DOTLR_PH]], !llvm.loop [[LOOP5:![0-9]+]]
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; CHECK: ._crit_edge.loopexit:
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; CHECK-NEXT: br label [[DOT_CRIT_EDGE]]
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; CHECK: ._crit_edge:
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; CHECK-NEXT: ret i32 undef
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;
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%1 = icmp sgt i32 %n, 9
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br i1 %1, label %.lr.ph, label %._crit_edge
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