forked from OSchip/llvm-project
[GlobalISel] CSEMIRBuilder: Add support for G_GEP
Summary: This patch adds G_GEP to `shouldCSEOpc` so that it can be CSEd. It also refactors `translateGetElementPtr` by replacing `createGenericVirtualRegister` calls with types. Reviewers: aditya_nandakumar, arsenm, dsanders, paquette, aemerson Reviewed By: aditya_nandakumar Subscribers: wdng, rovka, javed.absar, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D66316 llvm-svn: 369070
This commit is contained in:
Volkan Keles
parent
9b9a308452
commit
0ae6006bee
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@ -52,6 +52,7 @@ bool CSEConfigFull::shouldCSEOpc(unsigned Opc) {
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case TargetOpcode::G_ANYEXT:
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case TargetOpcode::G_UNMERGE_VALUES:
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case TargetOpcode::G_TRUNC:
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case TargetOpcode::G_GEP:
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return true;
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}
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return false;
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@ -1076,36 +1076,29 @@ bool IRTranslator::translateGetElementPtr(const User &U,
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}
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if (Offset != 0) {
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Register NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
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LLT OffsetTy = getLLTForType(*OffsetIRTy, *DL);
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auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset);
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MIRBuilder.buildGEP(NewBaseReg, BaseReg, OffsetMIB.getReg(0));
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BaseReg = NewBaseReg;
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BaseReg =
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MIRBuilder.buildGEP(PtrTy, BaseReg, OffsetMIB.getReg(0)).getReg(0);
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Offset = 0;
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}
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Register IdxReg = getOrCreateVReg(*Idx);
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if (MRI->getType(IdxReg) != OffsetTy) {
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Register NewIdxReg = MRI->createGenericVirtualRegister(OffsetTy);
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MIRBuilder.buildSExtOrTrunc(NewIdxReg, IdxReg);
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IdxReg = NewIdxReg;
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}
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if (MRI->getType(IdxReg) != OffsetTy)
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IdxReg = MIRBuilder.buildSExtOrTrunc(OffsetTy, IdxReg).getReg(0);
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// N = N + Idx * ElementSize;
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// Avoid doing it for ElementSize of 1.
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Register GepOffsetReg;
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if (ElementSize != 1) {
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GepOffsetReg = MRI->createGenericVirtualRegister(OffsetTy);
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auto ElementSizeMIB = MIRBuilder.buildConstant(
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getLLTForType(*OffsetIRTy, *DL), ElementSize);
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MIRBuilder.buildMul(GepOffsetReg, ElementSizeMIB.getReg(0), IdxReg);
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GepOffsetReg =
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MIRBuilder.buildMul(OffsetTy, ElementSizeMIB, IdxReg).getReg(0);
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} else
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GepOffsetReg = IdxReg;
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Register NewBaseReg = MRI->createGenericVirtualRegister(PtrTy);
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MIRBuilder.buildGEP(NewBaseReg, BaseReg, GepOffsetReg);
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BaseReg = NewBaseReg;
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BaseReg = MIRBuilder.buildGEP(PtrTy, BaseReg, GepOffsetReg).getReg(0);
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}
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}
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@ -207,11 +207,7 @@ MachineInstrBuilder MachineIRBuilder::buildGEP(const DstOp &Res,
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Res.getLLTTy(*getMRI()) == Op0.getLLTTy(*getMRI()) && "type mismatch");
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assert(Op1.getLLTTy(*getMRI()).isScalar() && "invalid offset type");
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auto MIB = buildInstr(TargetOpcode::G_GEP);
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Res.addDefToMIB(*getMRI(), MIB);
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Op0.addSrcToMIB(MIB);
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Op1.addSrcToMIB(MIB);
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return MIB;
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return buildInstr(TargetOpcode::G_GEP, {Res}, {Op0, Op1});
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}
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Optional<MachineInstrBuilder>
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@ -0,0 +1,51 @@
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; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O0
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; RUN: llc -O3 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s --check-prefix=O3
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target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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target triple = "aarch64--"
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define i32 @cse_gep([4 x i32]* %ptr, i32 %idx) {
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; O0-LABEL: name: cse_gep
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; O0: bb.1 (%ir-block.0):
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; O0: liveins: $w1, $x0
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; O0: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; O0: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; O0: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
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; O0: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; O0: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[SEXT]]
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; O0: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[MUL]](s64)
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; O0: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP]](p0)
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; O0: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load 4 from %ir.gep1)
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; O0: [[MUL1:%[0-9]+]]:_(s64) = G_MUL [[C]], [[SEXT]]
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; O0: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[MUL1]](s64)
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; O0: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
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; O0: [[GEP2:%[0-9]+]]:_(p0) = G_GEP [[GEP1]], [[C1]](s64)
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; O0: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP2]](p0) :: (load 4 from %ir.gep2)
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; O0: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[LOAD1]]
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; O0: $w0 = COPY [[ADD]](s32)
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; O0: RET_ReallyLR implicit $w0
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; O3-LABEL: name: cse_gep
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; O3: bb.1 (%ir-block.0):
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; O3: liveins: $w1, $x0
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; O3: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
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; O3: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
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; O3: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[COPY1]](s32)
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; O3: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
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; O3: [[MUL:%[0-9]+]]:_(s64) = G_MUL [[C]], [[SEXT]]
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; O3: [[GEP:%[0-9]+]]:_(p0) = G_GEP [[COPY]], [[MUL]](s64)
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; O3: [[COPY2:%[0-9]+]]:_(p0) = COPY [[GEP]](p0)
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; O3: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY2]](p0) :: (load 4 from %ir.gep1)
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; O3: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
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; O3: [[GEP1:%[0-9]+]]:_(p0) = G_GEP [[GEP]], [[C1]](s64)
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; O3: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[GEP1]](p0) :: (load 4 from %ir.gep2)
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; O3: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[LOAD1]], [[LOAD1]]
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; O3: $w0 = COPY [[ADD]](s32)
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; O3: RET_ReallyLR implicit $w0
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%sidx = sext i32 %idx to i64
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%gep1 = getelementptr inbounds [4 x i32], [4 x i32]* %ptr, i64 %sidx, i64 0
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%v1 = load i32, i32* %gep1
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%gep2 = getelementptr inbounds [4 x i32], [4 x i32]* %ptr, i64 %sidx, i64 1
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%v2 = load i32, i32* %gep2
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%res = add i32 %v2, %v2
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ret i32 %res
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}
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@ -560,8 +560,8 @@ define void @test_load_store_struct({i32, i32} *%addr) {
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; CHECK-DAG: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFFSET]](s32)
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; CHECK-DAG: [[VAL2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4 from %ir.addr + 4)
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; CHECK-DAG: G_STORE [[VAL1]](s32), [[ADDR1]](p0) :: (store 4 into %ir.addr)
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; CHECK-DAG: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFFSET]](s32)
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; CHECK-DAG: G_STORE [[VAL2]](s32), [[ADDR2]](p0) :: (store 4 into %ir.addr + 4)
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; CHECK-DAG: [[ADDR3:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
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; CHECK-DAG: G_STORE [[VAL2]](s32), [[ADDR3]](p0) :: (store 4 into %ir.addr + 4)
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%val = load {i32, i32}, {i32, i32} *%addr, align 4
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store {i32, i32} %val, {i32, i32} *%addr, align 4
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ret void
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@ -109,9 +109,9 @@ body: |
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; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4, align 1)
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; CHECK-NEXT: [[OFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
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; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4, align 1)
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
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; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4, align 1)
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; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1)
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; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
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; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4, align 1)
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%0(p0) = COPY $r0
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%1(s64) = G_LOAD %0(p0) :: (load 8, align 1)
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@ -146,19 +146,19 @@ body: |
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; CHECK-NEXT: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4, align 1)
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; CHECK-NEXT: [[OFF:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
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; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4, align 1)
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
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; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4, align 1)
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; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4, align 1)
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; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
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; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4, align 1)
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
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; CHECK-NEXT: G_STORE [[V2]](s32), [[COPY2]](p0) :: (store 4, align 1)
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%0(p0) = COPY $r0
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%1(s64) = G_LOAD %0(p0) :: (load 8, align 1)
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G_STORE %1(s64), %0(p0) :: (store 8, align 1)
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; CHECK: [[V1:%[0-9]+]]:_(s32) = G_LOAD [[ADDR1]](p0) :: (load 4)
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; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
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; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[ADDR2]](p0) :: (load 4)
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(p0) = COPY [[ADDR2]]
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; CHECK-NEXT: [[V2:%[0-9]+]]:_(s32) = G_LOAD [[COPY3]](p0) :: (load 4)
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; CHECK-NEXT: G_STORE [[V1]](s32), [[ADDR1]](p0) :: (store 4)
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; CHECK-NEXT: [[ADDR2:%[0-9]+]]:_(p0) = G_GEP [[ADDR1]], [[OFF]]
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; CHECK-NEXT: G_STORE [[V2]](s32), [[ADDR2]](p0) :: (store 4)
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%2(s64) = G_LOAD %0(p0) :: (load 8, align 4)
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G_STORE %2(s64), %0(p0) :: (store 8, align 4)
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