forked from OSchip/llvm-project
Merge the duplicated iabs optimization in DAGCombiner and let it detected a few more idioms.
llvm-svn: 107868
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@ -6892,38 +6892,34 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1,
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}
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}
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}
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}
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// Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
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// Check to see if this is an integer abs.
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// select_cc setg[te] X, 0, X, -X ->
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// select_cc setgt X, -1, X, -X ->
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// select_cc setl[te] X, 0, -X, X ->
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// select_cc setlt X, 1, -X, X ->
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// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
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// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
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if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
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if (N1C) {
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N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
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ConstantSDNode *SubC = NULL;
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N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
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if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
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(N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
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N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
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SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
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else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
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(N1C->isOne() && CC == ISD::SETLT)) &&
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N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
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SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
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EVT XType = N0.getValueType();
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EVT XType = N0.getValueType();
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SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
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if (SubC && SubC->isNullValue() && XType.isInteger()) {
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DAG.getConstant(XType.getSizeInBits()-1,
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SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
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getShiftAmountTy()));
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N0,
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SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType,
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DAG.getConstant(XType.getSizeInBits()-1,
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N0, Shift);
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getShiftAmountTy()));
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AddToWorkList(Shift.getNode());
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SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
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AddToWorkList(Add.getNode());
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XType, N0, Shift);
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return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
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AddToWorkList(Shift.getNode());
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}
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AddToWorkList(Add.getNode());
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// Check to see if this is an integer abs. select_cc setgt X, -1, X, -X ->
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return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
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// Y = sra (X, size(X)-1); xor (add (X, Y), Y)
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if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
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N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
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if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
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EVT XType = N0.getValueType();
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if (SubC->isNullValue() && XType.isInteger()) {
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SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
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N0,
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DAG.getConstant(XType.getSizeInBits()-1,
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getShiftAmountTy()));
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SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(),
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XType, N0, Shift);
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AddToWorkList(Shift.getNode());
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AddToWorkList(Add.getNode());
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return DAG.getNode(ISD::XOR, DL, XType, Add, Shift);
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}
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}
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}
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}
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}
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