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[Intrinsic] Unigned Saturation Addition Intrinsic 

Add an intrinsic that takes 2 integers and perform unsigned saturation
addition on them.

This is a part of implementing fixed point arithmetic in clang where some of
the more complex operations will be implemented as intrinsics.

Differential Revision: https://reviews.llvm.org/D53340

llvm-svn: 344971
This commit is contained in:
Leonard Chan 2018-10-22 23:08:40 +00:00
parent a0beeffeed
commit 0acfc6be38
15 changed files with 237 additions and 49 deletions
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8
llvm/include/llvm/CodeGen/ISDOpcodes.h
View File

@ -256,13 +256,13 @@ namespace ISD {
/// Same for multiplication.
SMULO, UMULO,
/// RESULT = SADDSAT(LHS, RHS) - Perform signed saturation addition on 2
/// RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2
/// integers with the same bit width (W). If the true value of LHS + RHS
/// exceeds the largest signed value that can be represented by W bits, the
/// exceeds the largest value that can be represented by W bits, the
/// resulting value is this maximum value. Otherwise, if this value is less
/// than the smallest signed value that can be represented by W bits, the
/// than the smallest value that can be represented by W bits, the
/// resulting value is this minimum value.
SADDSAT,
SADDSAT, UADDSAT,
/// Simple binary floating point operators.
FADD, FSUB, FMUL, FDIV, FREM,

7
llvm/include/llvm/CodeGen/TargetLowering.h
View File

@ -3684,10 +3684,9 @@ public:
SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
SDValue Index) const;
/// Method for building the DAG expansion of ISD::SADDSAT. This method accepts
/// integers or vectors of integers as its arguments.
SDValue getExpandedSignedSaturationAddition(SDNode *Node,
SelectionDAG &DAG) const;
/// Method for building the DAG expansion of ISD::[US]ADDSAT. This method
/// accepts integers or vectors of integers as its arguments.
SDValue getExpandedSaturationAddition(SDNode *Node, SelectionDAG &DAG) const;
//===--------------------------------------------------------------------===//
// Instruction Emitting Hooks

3
llvm/include/llvm/IR/Intrinsics.td
View File

@ -713,6 +713,9 @@ def int_umul_with_overflow : Intrinsic<[llvm_anyint_ty, llvm_i1_ty],
def int_sadd_sat : Intrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable, Commutative]>;
def int_uadd_sat : Intrinsic<[llvm_anyint_ty],
[LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable, Commutative]>;
//===------------------------- Memory Use Markers -------------------------===//
//

1
llvm/include/llvm/Target/TargetSelectionDAG.td
View File

@ -374,6 +374,7 @@ def umax : SDNode<"ISD::UMAX" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
def uaddsat : SDNode<"ISD::UADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>;

8
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -1115,7 +1115,8 @@ void SelectionDAGLegalize::LegalizeOp(SDNode *Node) {
Action = TLI.getStrictFPOperationAction(Node->getOpcode(),
Node->getValueType(0));
break;
case ISD::SADDSAT: {
case ISD::SADDSAT:
case ISD::UADDSAT: {
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
break;
}
@ -3460,8 +3461,9 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
}
break;
}
case ISD::SADDSAT: {
Results.push_back(TLI.getExpandedSignedSaturationAddition(Node, DAG));
case ISD::SADDSAT:
case ISD::UADDSAT: {
Results.push_back(TLI.getExpandedSaturationAddition(Node, DAG));
break;
}
case ISD::SADDO:

27
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -141,7 +141,8 @@ void DAGTypeLegalizer::PromoteIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::ADDCARRY:
case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
case ISD::SADDSAT: Res = PromoteIntRes_SADDSAT(N); break;
case ISD::SADDSAT:
case ISD::UADDSAT: Res = PromoteIntRes_ADDSAT(N); break;
case ISD::ATOMIC_LOAD:
Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
@ -548,17 +549,22 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
return SDValue(Res.getNode(), 1);
}
SDValue DAGTypeLegalizer::PromoteIntRes_SADDSAT(SDNode *N) {
SDValue DAGTypeLegalizer::PromoteIntRes_ADDSAT(SDNode *N) {
// For promoting iN -> iM, this can be expanded by
// 1. ANY_EXTEND iN to iM
// 2. SHL by M-N
// 3. SADDSAT
// 4. ASHR by M-N
// 3. U/SADDSAT
// 4. L/ASHR by M-N
SDLoc dl(N);
SDValue Op1 = N->getOperand(0);
SDValue Op2 = N->getOperand(1);
unsigned OldBits = Op1.getValueSizeInBits();
unsigned Opcode = N->getOpcode();
assert((Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT) &&
"Expected opcode to be SADDSAT or UADDSAT");
unsigned ShiftOp = Opcode == ISD::SADDSAT ? ISD::SRA : ISD::SRL;
SDValue Op1Promoted = GetPromotedInteger(Op1);
SDValue Op2Promoted = GetPromotedInteger(Op2);
@ -573,8 +579,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SADDSAT(SDNode *N) {
DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
SDValue Result =
DAG.getNode(ISD::SADDSAT, dl, PromotedType, Op1Promoted, Op2Promoted);
return DAG.getNode(ISD::SRA, dl, PromotedType, Result, ShiftAmount);
DAG.getNode(Opcode, dl, PromotedType, Op1Promoted, Op2Promoted);
return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
}
SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
@ -1498,7 +1504,8 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::UMULO:
case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
case ISD::SADDSAT: ExpandIntRes_SADDSAT(N, Lo, Hi); break;
case ISD::SADDSAT:
case ISD::UADDSAT: ExpandIntRes_ADDSAT(N, Lo, Hi); break;
}
// If Lo/Hi is null, the sub-method took care of registering results etc.
@ -2461,9 +2468,9 @@ void DAGTypeLegalizer::ExpandIntRes_READCYCLECOUNTER(SDNode *N, SDValue &Lo,
ReplaceValueWith(SDValue(N, 1), R.getValue(2));
}
void DAGTypeLegalizer::ExpandIntRes_SADDSAT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue Result = TLI.getExpandedSignedSaturationAddition(N, DAG);
void DAGTypeLegalizer::ExpandIntRes_ADDSAT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
SDValue Result = TLI.getExpandedSaturationAddition(N, DAG);
SplitInteger(Result, Lo, Hi);
}

4
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
View File

@ -330,7 +330,7 @@ private:
SDValue PromoteIntRes_UNDEF(SDNode *N);
SDValue PromoteIntRes_VAARG(SDNode *N);
SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
SDValue PromoteIntRes_SADDSAT(SDNode *N);
SDValue PromoteIntRes_ADDSAT(SDNode *N);
// Integer Operand Promotion.
bool PromoteIntegerOperand(SDNode *N, unsigned OpNo);
@ -415,7 +415,7 @@ private:
void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_SADDSAT (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_ADDSAT (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_ATOMIC_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);

1
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
View File

@ -390,6 +390,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) {
case ISD::UMUL_LOHI:
case ISD::FCANONICALIZE:
case ISD::SADDSAT:
case ISD::UADDSAT:
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
break;
case ISD::FP_ROUND_INREG:

2
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -123,6 +123,7 @@ void DAGTypeLegalizer::ScalarizeVectorResult(SDNode *N, unsigned ResNo) {
case ISD::UMAX:
case ISD::SADDSAT:
case ISD::UADDSAT:
case ISD::FPOW:
case ISD::FREM:
@ -805,6 +806,7 @@ void DAGTypeLegalizer::SplitVectorResult(SDNode *N, unsigned ResNo) {
case ISD::UMIN:
case ISD::UMAX:
case ISD::SADDSAT:
case ISD::UADDSAT:
SplitVecRes_BinOp(N, Lo, Hi);
break;
case ISD::FMA:

6
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -5777,6 +5777,12 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2));
return nullptr;
}
case Intrinsic::uadd_sat: {
SDValue Op1 = getValue(I.getArgOperand(0));
SDValue Op2 = getValue(I.getArgOperand(1));
setValue(&I, DAG.getNode(ISD::UADDSAT, sdl, Op1.getValueType(), Op1, Op2));
return nullptr;
}
case Intrinsic::stacksave: {
SDValue Op = getRoot();
Res = DAG.getNode(

1
llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
View File

@ -286,6 +286,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const {
case ISD::SRL_PARTS: return "srl_parts";
case ISD::SADDSAT: return "saddsat";
case ISD::UADDSAT: return "uaddsat";
// Conversion operators.
case ISD::SIGN_EXTEND: return "sign_extend";

47
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -4681,13 +4681,12 @@ SDValue TargetLowering::lowerCmpEqZeroToCtlzSrl(SDValue Op,
return SDValue();
}
SDValue
TargetLowering::getExpandedSignedSaturationAddition(SDNode *Node,
SelectionDAG &DAG) const {
assert(Node->getOpcode() == ISD::SADDSAT &&
"Expected method to receive SADDSAT node.");
assert(Node->getNumOperands() == 2 &&
"Expected SADDSAT node to have 2 operands.");
SDValue TargetLowering::getExpandedSaturationAddition(SDNode *Node,
SelectionDAG &DAG) const {
unsigned Opcode = Node->getOpcode();
assert((Opcode == ISD::SADDSAT || Opcode == ISD::UADDSAT) &&
"Expected method to receive SADDSAT or UADDSAT node.");
assert(Node->getNumOperands() == 2 && "Expected node to have 2 operands.");
SDLoc dl(Node);
SDValue LHS = Node->getOperand(0);
@ -4699,27 +4698,33 @@ TargetLowering::getExpandedSignedSaturationAddition(SDNode *Node,
"Expected operands to be integers. Vector of int arguments should "
"already be unrolled.");
assert(LHS.getValueType() == RHS.getValueType() &&
"Expected both operands of SADDSAT to be the same type");
"Expected both operands to be the same type");
unsigned OverflowOp = Opcode == ISD::SADDSAT ? ISD::SADDO : ISD::UADDO;
unsigned BitWidth = LHS.getValueSizeInBits();
EVT ResultType = LHS.getValueType();
EVT BoolVT =
getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), ResultType);
SDValue Result =
DAG.getNode(ISD::SADDO, dl, DAG.getVTList(ResultType, BoolVT), LHS, RHS);
DAG.getNode(OverflowOp, dl, DAG.getVTList(ResultType, BoolVT), LHS, RHS);
SDValue Sum = Result.getValue(0);
SDValue Overflow = Result.getValue(1);
SDValue Zero = DAG.getConstant(0, dl, ResultType);
// SatMax -> Overflow && Sum < 0
// SatMin -> Overflow && Sum > 0
SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
SDValue SumNeg = DAG.getSetCC(dl, BoolVT, Sum, Zero, ISD::SETLT);
APInt MinVal = APInt::getSignedMinValue(BitWidth);
APInt MaxVal = APInt::getSignedMaxValue(BitWidth);
SDValue SatMin = DAG.getConstant(MinVal, dl, ResultType);
SDValue SatMax = DAG.getConstant(MaxVal, dl, ResultType);
Result = DAG.getSelect(dl, ResultType, SumNeg, SatMax, SatMin);
return DAG.getSelect(dl, ResultType, Overflow, Result, Sum);
if (Opcode == ISD::SADDSAT) {
// SatMax -> Overflow && Sum < 0
// SatMin -> Overflow && Sum > 0
APInt MinVal = APInt::getSignedMinValue(BitWidth);
APInt MaxVal = APInt::getSignedMaxValue(BitWidth);
SDValue SatMin = DAG.getConstant(MinVal, dl, ResultType);
SDValue SatMax = DAG.getConstant(MaxVal, dl, ResultType);
SDValue SumNeg = DAG.getSetCC(dl, BoolVT, Sum, Zero, ISD::SETLT);
Result = DAG.getSelect(dl, ResultType, SumNeg, SatMax, SatMin);
return DAG.getSelect(dl, ResultType, Overflow, Result, Sum);
} else {
// Just need to check overflow for SatMax.
APInt MaxVal = APInt::getMaxValue(BitWidth);
SDValue SatMax = DAG.getConstant(MaxVal, dl, ResultType);
return DAG.getSelect(dl, ResultType, Overflow, SatMax, Sum);
}
}

1
llvm/lib/CodeGen/TargetLoweringBase.cpp
View File

@ -611,6 +611,7 @@ void TargetLoweringBase::initActions() {
setOperationAction(ISD::UMAX, VT, Expand);
setOperationAction(ISD::ABS, VT, Expand);
setOperationAction(ISD::SADDSAT, VT, Expand);
setOperationAction(ISD::UADDSAT, VT, Expand);
// Overflow operations default to expand
setOperationAction(ISD::SADDO, VT, Expand);

13
llvm/lib/IR/Verifier.cpp
View File

@ -4474,13 +4474,16 @@ void Verifier::visitIntrinsicCallSite(Intrinsic::ID ID, CallSite CS) {
break;
}
case Intrinsic::sadd_sat: {
case Intrinsic::sadd_sat:
case Intrinsic::uadd_sat: {
Value *Op1 = CS.getArgOperand(0);
Value *Op2 = CS.getArgOperand(1);
Assert(Op1->getType()->isIntOrIntVectorTy(),
"first operand of sadd_sat must be an int type or vector of ints");
Assert(Op2->getType()->isIntOrIntVectorTy(),
"second operand of sadd_sat must be an int type or vector of ints");
Assert(
Op1->getType()->isIntOrIntVectorTy(),
"first operand of [us]add_sat must be an int type or vector of ints");
Assert(
Op2->getType()->isIntOrIntVectorTy(),
"second operand of [us]add_sat must be an int type or vector of ints");
break;
}
};

157
llvm/test/CodeGen/X86/uadd_sat.ll Normal file
View File

@ -0,0 +1,157 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
; RUN: llc < %s -mcpu=generic -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefix=CHECK32
declare i4 @llvm.uadd.sat.i4 (i4, i4)
declare i32 @llvm.uadd.sat.i32 (i32, i32)
declare i64 @llvm.uadd.sat.i64 (i64, i64)
declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)
define i32 @func(i32 %x, i32 %y) {
; CHECK-LABEL: func:
; CHECK: # %bb.0:
; CHECK-NEXT: addl %esi, %edi
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: cmovael %edi, %eax
; CHECK-NEXT: retq
;
; CHECK32-LABEL: func:
; CHECK32: # %bb.0:
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl $-1, %eax
; CHECK32-NEXT: cmovael %ecx, %eax
; CHECK32-NEXT: retl
%tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y);
ret i32 %tmp;
}
define i64 @func2(i64 %x, i64 %y) {
; CHECK-LABEL: func2:
; CHECK: # %bb.0:
; CHECK-NEXT: addq %rsi, %rdi
; CHECK-NEXT: movq $-1, %rax
; CHECK-NEXT: cmovaeq %rdi, %rax
; CHECK-NEXT: retq
;
; CHECK32-LABEL: func2:
; CHECK32: # %bb.0:
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: adcl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl $-1, %ecx
; CHECK32-NEXT: cmovbl %ecx, %edx
; CHECK32-NEXT: cmovbl %ecx, %eax
; CHECK32-NEXT: retl
%tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %y);
ret i64 %tmp;
}
define i4 @func3(i4 %x, i4 %y) {
; CHECK-LABEL: func3:
; CHECK: # %bb.0:
; CHECK-NEXT: shlb $4, %sil
; CHECK-NEXT: shlb $4, %dil
; CHECK-NEXT: addb %sil, %dil
; CHECK-NEXT: movb $-1, %al
; CHECK-NEXT: jb .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: shrb $4, %al
; CHECK-NEXT: retq
;
; CHECK32-LABEL: func3:
; CHECK32: # %bb.0:
; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al
; CHECK32-NEXT: shlb $4, %al
; CHECK32-NEXT: shlb $4, %cl
; CHECK32-NEXT: addb %al, %cl
; CHECK32-NEXT: movb $-1, %al
; CHECK32-NEXT: jb .LBB2_2
; CHECK32-NEXT: # %bb.1:
; CHECK32-NEXT: movl %ecx, %eax
; CHECK32-NEXT: .LBB2_2:
; CHECK32-NEXT: shrb $4, %al
; CHECK32-NEXT: retl
%tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y);
ret i4 %tmp;
}
define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) {
; CHECK-LABEL: vec:
; CHECK: # %bb.0:
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3]
; CHECK-NEXT: movd %xmm2, %eax
; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3]
; CHECK-NEXT: movd %xmm2, %ecx
; CHECK-NEXT: addl %eax, %ecx
; CHECK-NEXT: movl $-1, %eax
; CHECK-NEXT: cmovbl %eax, %ecx
; CHECK-NEXT: movd %ecx, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
; CHECK-NEXT: movd %xmm3, %ecx
; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
; CHECK-NEXT: movd %xmm3, %edx
; CHECK-NEXT: addl %ecx, %edx
; CHECK-NEXT: cmovbl %eax, %edx
; CHECK-NEXT: movd %edx, %xmm3
; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
; CHECK-NEXT: movd %xmm1, %ecx
; CHECK-NEXT: movd %xmm0, %edx
; CHECK-NEXT: addl %ecx, %edx
; CHECK-NEXT: cmovbl %eax, %edx
; CHECK-NEXT: movd %edx, %xmm2
; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3]
; CHECK-NEXT: movd %xmm1, %ecx
; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
; CHECK-NEXT: movd %xmm0, %edx
; CHECK-NEXT: addl %ecx, %edx
; CHECK-NEXT: cmovbl %eax, %edx
; CHECK-NEXT: movd %edx, %xmm0
; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
; CHECK-NEXT: movdqa %xmm2, %xmm0
; CHECK-NEXT: retq
;
; CHECK32-LABEL: vec:
; CHECK32: # %bb.0:
; CHECK32-NEXT: pushl %ebx
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: pushl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: pushl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 16
; CHECK32-NEXT: .cfi_offset %esi, -16
; CHECK32-NEXT: .cfi_offset %edi, -12
; CHECK32-NEXT: .cfi_offset %ebx, -8
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %edi
; CHECK32-NEXT: movl $-1, %ebx
; CHECK32-NEXT: cmovbl %ebx, %edi
; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %esi
; CHECK32-NEXT: cmovbl %ebx, %esi
; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %edx
; CHECK32-NEXT: cmovbl %ebx, %edx
; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %ecx
; CHECK32-NEXT: cmovbl %ebx, %ecx
; CHECK32-NEXT: movl %ecx, 12(%eax)
; CHECK32-NEXT: movl %edx, 8(%eax)
; CHECK32-NEXT: movl %esi, 4(%eax)
; CHECK32-NEXT: movl %edi, (%eax)
; CHECK32-NEXT: popl %esi
; CHECK32-NEXT: .cfi_def_cfa_offset 12
; CHECK32-NEXT: popl %edi
; CHECK32-NEXT: .cfi_def_cfa_offset 8
; CHECK32-NEXT: popl %ebx
; CHECK32-NEXT: .cfi_def_cfa_offset 4
; CHECK32-NEXT: retl $4
%tmp = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
ret <4 x i32> %tmp;
}