forked from OSchip/llvm-project
ARM64: print lsr instead of lsrv for variable shifts (etc)
The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
This commit is contained in:
Tim Northover
parent
7030f05b4f
commit
0ac99404f0
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@ -544,19 +544,19 @@ defm SDIV_Int : Div<1, "sdiv", int_arm64_sdiv>;
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}
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// Variable shift
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defm ASRV : Shift<0b10, "asrv", sra>;
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defm LSLV : Shift<0b00, "lslv", shl>;
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defm LSRV : Shift<0b01, "lsrv", srl>;
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defm RORV : Shift<0b11, "rorv", rotr>;
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defm ASRV : Shift<0b10, "asr", sra>;
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defm LSLV : Shift<0b00, "lsl", shl>;
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defm LSRV : Shift<0b01, "lsr", srl>;
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defm RORV : Shift<0b11, "ror", rotr>;
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def : ShiftAlias<"asr", ASRVWr, GPR32>;
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def : ShiftAlias<"asr", ASRVXr, GPR64>;
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def : ShiftAlias<"lsl", LSLVWr, GPR32>;
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def : ShiftAlias<"lsl", LSLVXr, GPR64>;
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def : ShiftAlias<"lsr", LSRVWr, GPR32>;
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def : ShiftAlias<"lsr", LSRVXr, GPR64>;
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def : ShiftAlias<"ror", RORVWr, GPR32>;
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def : ShiftAlias<"ror", RORVXr, GPR64>;
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def : ShiftAlias<"asrv", ASRVWr, GPR32>;
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def : ShiftAlias<"asrv", ASRVXr, GPR64>;
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def : ShiftAlias<"lslv", LSLVWr, GPR32>;
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def : ShiftAlias<"lslv", LSLVXr, GPR64>;
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def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
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def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
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def : ShiftAlias<"rorv", RORVWr, GPR32>;
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def : ShiftAlias<"rorv", RORVXr, GPR64>;
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// Multiply-add
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let AddedComplexity = 7 in {
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@ -48,7 +48,7 @@ entry:
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define i32 @t6(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t6:
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; CHECK: lslv w0, w0, w1
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; CHECK: lsl w0, w0, w1
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; CHECK: ret
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%shl = shl i32 %a, %b
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ret i32 %shl
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@ -57,7 +57,7 @@ entry:
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define i64 @t7(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t7:
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; CHECK: lslv x0, x0, x1
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; CHECK: lsl x0, x0, x1
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; CHECK: ret
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%shl = shl i64 %a, %b
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ret i64 %shl
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@ -66,7 +66,7 @@ entry:
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define i32 @t8(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t8:
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; CHECK: lsrv w0, w0, w1
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; CHECK: lsr w0, w0, w1
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; CHECK: ret
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%lshr = lshr i32 %a, %b
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ret i32 %lshr
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@ -75,7 +75,7 @@ entry:
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define i64 @t9(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t9:
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; CHECK: lsrv x0, x0, x1
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; CHECK: lsr x0, x0, x1
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; CHECK: ret
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%lshr = lshr i64 %a, %b
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ret i64 %lshr
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@ -84,7 +84,7 @@ entry:
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define i32 @t10(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t10:
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; CHECK: asrv w0, w0, w1
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; CHECK: asr w0, w0, w1
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; CHECK: ret
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%ashr = ashr i32 %a, %b
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ret i32 %ashr
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@ -93,7 +93,7 @@ entry:
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define i64 @t11(i64 %a, i64 %b) nounwind readnone ssp {
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entry:
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; CHECK-LABEL: t11:
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; CHECK: asrv x0, x0, x1
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; CHECK: asr x0, x0, x1
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; CHECK: ret
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%ashr = ashr i64 %a, %b
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ret i64 %ashr
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@ -2,16 +2,16 @@
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define i128 @shl(i128 %r, i128 %s) nounwind readnone {
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; CHECK-LABEL: shl:
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; CHECK: lslv [[XREG_0:x[0-9]+]], x1, x2
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; CHECK: lsl [[XREG_0:x[0-9]+]], x1, x2
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; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
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; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
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; CHECK-NEXT: lsrv [[XREG_3:x[0-9]+]], x0, [[XREG_2]]
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; CHECK-NEXT: lsr [[XREG_3:x[0-9]+]], x0, [[XREG_2]]
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; CHECK-NEXT: orr [[XREG_6:x[0-9]+]], [[XREG_3]], [[XREG_0]]
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; CHECK-NEXT: sub [[XREG_4:x[0-9]+]], x2, #64
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; CHECK-NEXT: lslv [[XREG_5:x[0-9]+]], x0, [[XREG_4]]
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; CHECK-NEXT: lsl [[XREG_5:x[0-9]+]], x0, [[XREG_4]]
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; CHECK-NEXT: cmp [[XREG_4]], #0
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; CHECK-NEXT: csel x1, [[XREG_5]], [[XREG_6]], ge
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; CHECK-NEXT: lslv [[SMALLSHIFT_LO:x[0-9]+]], x0, x2
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; CHECK-NEXT: lsl [[SMALLSHIFT_LO:x[0-9]+]], x0, x2
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; CHECK-NEXT: csel x0, xzr, [[SMALLSHIFT_LO]], ge
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; CHECK-NEXT: ret
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@ -21,16 +21,16 @@ define i128 @shl(i128 %r, i128 %s) nounwind readnone {
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define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
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; CHECK-LABEL: ashr:
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; CHECK: lsrv [[XREG_0:x[0-9]+]], x0, x2
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; CHECK: lsr [[XREG_0:x[0-9]+]], x0, x2
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; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
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; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
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; CHECK-NEXT: lslv [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
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; CHECK-NEXT: lsl [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
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; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
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; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
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; CHECK-NEXT: asrv [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
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; CHECK-NEXT: asr [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
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; CHECK-NEXT: cmp [[XREG_5]], #0
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; CHECK-NEXT: csel x0, [[XREG_6]], [[XREG_4]], ge
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; CHECK-NEXT: asrv [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
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; CHECK-NEXT: asr [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
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; CHECK-NEXT: asr [[BIGSHIFT_HI:x[0-9]+]], x1, #63
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; CHECK-NEXT: csel x1, [[BIGSHIFT_HI]], [[SMALLSHIFT_HI]], ge
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; CHECK-NEXT: ret
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@ -41,16 +41,16 @@ define i128 @ashr(i128 %r, i128 %s) nounwind readnone {
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define i128 @lshr(i128 %r, i128 %s) nounwind readnone {
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; CHECK-LABEL: lshr:
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; CHECK: lsrv [[XREG_0:x[0-9]+]], x0, x2
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; CHECK: lsr [[XREG_0:x[0-9]+]], x0, x2
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; CHECK-NEXT: orr w[[XREG_1:[0-9]+]], wzr, #0x40
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; CHECK-NEXT: sub [[XREG_2:x[0-9]+]], x[[XREG_1]], x2
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; CHECK-NEXT: lslv [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
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; CHECK-NEXT: lsl [[XREG_3:x[0-9]+]], x1, [[XREG_2]]
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; CHECK-NEXT: orr [[XREG_4:x[0-9]+]], [[XREG_0]], [[XREG_3]]
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; CHECK-NEXT: sub [[XREG_5:x[0-9]+]], x2, #64
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; CHECK-NEXT: lsrv [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
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; CHECK-NEXT: lsr [[XREG_6:x[0-9]+]], x1, [[XREG_5]]
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; CHECK-NEXT: cmp [[XREG_5]], #0
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; CHECK-NEXT: csel x0, [[XREG_6]], [[XREG_4]], ge
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; CHECK-NEXT: lsrv [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
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; CHECK-NEXT: lsr [[SMALLSHIFT_HI:x[0-9]+]], x1, x2
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; CHECK-NEXT: csel x1, xzr, [[SMALLSHIFT_HI]], ge
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; CHECK-NEXT: ret
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@ -368,21 +368,21 @@
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#==---------------------------------------------------------------------------==
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0x41 0x28 0xc3 0x1a
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# CHECK: asrv w1, w2, w3
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# CHECK: asr w1, w2, w3
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0x41 0x28 0xc3 0x9a
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# CHECK: asrv x1, x2, x3
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# CHECK: asr x1, x2, x3
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0x41 0x20 0xc3 0x1a
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# CHECK: lslv w1, w2, w3
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# CHECK: lsl w1, w2, w3
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0x41 0x20 0xc3 0x9a
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# CHECK: lslv x1, x2, x3
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# CHECK: lsl x1, x2, x3
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0x41 0x24 0xc3 0x1a
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# CHECK: lsrv w1, w2, w3
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# CHECK: lsr w1, w2, w3
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0x41 0x24 0xc3 0x9a
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# CHECK: lsrv x1, x2, x3
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# CHECK: lsr x1, x2, x3
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0x41 0x2c 0xc3 0x1a
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# CHECK: rorv w1, w2, w3
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# CHECK: ror w1, w2, w3
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0x41 0x2c 0xc3 0x9a
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# CHECK: rorv x1, x2, x3
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# CHECK: ror x1, x2, x3
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#==---------------------------------------------------------------------------==
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# One operand instructions
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