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[Hexagon] Handle Hexagon-specific machine operand target flags in MIR 

llvm-svn: 307564
This commit is contained in:
Krzysztof Parzyszek 2017-07-10 18:31:02 +00:00
parent acefbcf38e
commit 0ac065f318
4 changed files with 99 additions and 4 deletions
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33
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
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@ -1726,6 +1726,39 @@ bool HexagonInstrInfo::getIncrementValue(const MachineInstr &MI,
return false;
}
std::pair<unsigned, unsigned>
HexagonInstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
return std::make_pair(TF & ~HexagonII::MO_Bitmasks,
TF & HexagonII::MO_Bitmasks);
}
ArrayRef<std::pair<unsigned, const char*>>
HexagonInstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
using namespace HexagonII;
static const std::pair<unsigned, const char*> Flags[] = {
{MO_PCREL, "hexagon-pcrel"},
{MO_GOT, "hexagon-got"},
{MO_LO16, "hexagon-lo16"},
{MO_HI16, "hexagon-hi16"},
{MO_GPREL, "hexagon-gprel"},
{MO_GDGOT, "hexagon-gdgot"},
{MO_GDPLT, "hexagon-gdplt"},
{MO_IE, "hexagon-ie"},
{MO_IEGOT, "hexagon-iegot"},
{MO_TPREL, "hexagon-tprel"}
};
return makeArrayRef(Flags);
}
ArrayRef<std::pair<unsigned, const char*>>
HexagonInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const {
using namespace HexagonII;
static const std::pair<unsigned, const char*> Flags[] = {
{HMOTF_ConstExtended, "hexagon-ext"}
};
return makeArrayRef(Flags);
}
unsigned HexagonInstrInfo::createVR(MachineFunction *MF, MVT VT) const {
MachineRegisterInfo &MRI = MF->getRegInfo();
const TargetRegisterClass *TRC;

21
llvm/lib/Target/Hexagon/HexagonInstrInfo.h
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@ -301,6 +301,27 @@ public:
const MachineInstr &UseMI,
unsigned UseIdx) const override;
/// Decompose the machine operand's target flags into two values - the direct
/// target flag value and any of bit flags that are applied.
std::pair<unsigned, unsigned>
decomposeMachineOperandsTargetFlags(unsigned TF) const override;
/// Return an array that contains the direct target flag values and their
/// names.
///
/// MIR Serialization is able to serialize only the target flags that are
/// defined by this method.
ArrayRef<std::pair<unsigned, const char *>>
getSerializableDirectMachineOperandTargetFlags() const override;
/// Return an array that contains the bitmask target flag values and their
/// names.
///
/// MIR Serialization is able to serialize only the target flags that are
/// defined by this method.
ArrayRef<std::pair<unsigned, const char *>>
getSerializableBitmaskMachineOperandTargetFlags() const override;
bool isTailCall(const MachineInstr &MI) const override;
/// HexagonInstrInfo specifics.

13
llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
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@ -169,8 +169,11 @@ namespace HexagonII {
// Hexagon specific MO operand flag mask.
enum HexagonMOTargetFlagVal {
//===------------------------------------------------------------------===//
// Hexagon Specific MachineOperand flags.
// Hexagon-specific MachineOperand target flags.
//
// When chaning these, make sure to update
// getSerializableDirectMachineOperandTargetFlags and
// getSerializableBitmaskMachineOperandTargetFlags if needed.
MO_NO_FLAG,
/// MO_PCREL - On a symbol operand, indicates a PC-relative relocation
@ -207,10 +210,12 @@ namespace HexagonII {
MO_TPREL,
// HMOTF_ConstExtended
// Addendum to abovem, indicates a const extended op
// Addendum to above, indicates a const extended op
// Can be used as a mask.
HMOTF_ConstExtended = 0x80
HMOTF_ConstExtended = 0x80,
// Union of all bitmasks (currently only HMOTF_ConstExtended).
MO_Bitmasks = HMOTF_ConstExtended
};
// Hexagon Sub-instruction classes.

36
llvm/test/CodeGen/MIR/Hexagon/target-flags.mir Normal file
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@ -0,0 +1,36 @@
# RUN: llc -march=hexagon -run-pass none -o - %s | FileCheck %s
---
name: fred
body: |
bb.0:
; CHECK: target-flags(hexagon-pcrel)
%r0 = A2_tfrsi target-flags (hexagon-pcrel) 0
; CHECK: target-flags(hexagon-got)
%r0 = A2_tfrsi target-flags (hexagon-got) 0
; CHECK: target-flags(hexagon-lo16)
%r0 = A2_tfrsi target-flags (hexagon-lo16) 0
; CHECK: target-flags(hexagon-hi16)
%r0 = A2_tfrsi target-flags (hexagon-hi16) 0
; CHECK: target-flags(hexagon-gprel)
%r0 = A2_tfrsi target-flags (hexagon-gprel) 0
; CHECK: target-flags(hexagon-gdgot)
%r0 = A2_tfrsi target-flags (hexagon-gdgot) 0
; CHECK: target-flags(hexagon-gdplt)
%r0 = A2_tfrsi target-flags (hexagon-gdplt) 0
; CHECK: target-flags(hexagon-ie)
%r0 = A2_tfrsi target-flags (hexagon-ie) 0
; CHECK: target-flags(hexagon-iegot)
%r0 = A2_tfrsi target-flags (hexagon-iegot) 0
; CHECK: target-flags(hexagon-tprel)
%r0 = A2_tfrsi target-flags (hexagon-tprel) 0
; CHECK: target-flags(hexagon-ext)
%r0 = A2_tfrsi target-flags (hexagon-ext) 0
; CHECK: target-flags(hexagon-pcrel, hexagon-ext)
%r0 = A2_tfrsi target-flags (hexagon-pcrel,hexagon-ext) 0
; CHECK: target-flags(hexagon-ie, hexagon-ext)
%r0 = A2_tfrsi target-flags (hexagon-ie,hexagon-ext) 0
...