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[RISCV] Use bitfields to shrink the size of the vector load/store intrinsics to pseudo instruction lookup tables.

This commit is contained in:
Craig Topper 2021-06-07 16:35:27 -07:00
parent 11539edf52
commit 0aa941654f
1 changed files with 37 additions and 37 deletions
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74
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
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@ -94,67 +94,67 @@ private:
namespace RISCV {
struct VLSEGPseudo {
uint8_t NF;
uint8_t Masked;
uint8_t Strided;
uint8_t FF;
uint8_t Log2SEW;
uint8_t LMUL;
uint16_t NF : 4;
uint16_t Masked : 1;
uint16_t Strided : 1;
uint16_t FF : 1;
uint16_t Log2SEW : 3;
uint16_t LMUL : 3;
uint16_t Pseudo;
};
struct VLXSEGPseudo {
uint8_t NF;
uint8_t Masked;
uint8_t Ordered;
uint8_t Log2SEW;
uint8_t LMUL;
uint8_t IndexLMUL;
uint16_t NF : 4;
uint16_t Masked : 1;
uint16_t Ordered : 1;
uint16_t Log2SEW : 3;
uint16_t LMUL : 3;
uint16_t IndexLMUL : 3;
uint16_t Pseudo;
};
struct VSSEGPseudo {
uint8_t NF;
uint8_t Masked;
uint8_t Strided;
uint8_t Log2SEW;
uint8_t LMUL;
uint16_t NF : 4;
uint16_t Masked : 1;
uint16_t Strided : 1;
uint16_t Log2SEW : 3;
uint16_t LMUL : 3;
uint16_t Pseudo;
};
struct VSXSEGPseudo {
uint8_t NF;
uint8_t Masked;
uint8_t Ordered;
uint8_t Log2SEW;
uint8_t LMUL;
uint8_t IndexLMUL;
uint16_t NF : 4;
uint16_t Masked : 1;
uint16_t Ordered : 1;
uint16_t Log2SEW : 3;
uint16_t LMUL : 3;
uint16_t IndexLMUL : 3;
uint16_t Pseudo;
};
struct VLEPseudo {
uint8_t Masked;
uint8_t Strided;
uint8_t FF;
uint8_t Log2SEW;
uint8_t LMUL;
uint16_t Masked : 1;
uint16_t Strided : 1;
uint16_t FF : 1;
uint16_t Log2SEW : 3;
uint16_t LMUL : 3;
uint16_t Pseudo;
};
struct VSEPseudo {
uint8_t Masked;
uint8_t Strided;
uint8_t Log2SEW;
uint8_t LMUL;
uint16_t Masked :1;
uint16_t Strided : 1;
uint16_t Log2SEW : 3;
uint16_t LMUL : 3;
uint16_t Pseudo;
};
struct VLX_VSXPseudo {
uint8_t Masked;
uint8_t Ordered;
uint8_t Log2SEW;
uint8_t LMUL;
uint8_t IndexLMUL;
uint16_t Masked : 1;
uint16_t Ordered : 1;
uint16_t Log2SEW : 3;
uint16_t LMUL : 3;
uint16_t IndexLMUL : 3;
uint16_t Pseudo;
};