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This checkin represents some cleanup of the backend, implementing the following things: 

1. The TargetMachine structure is free to decide the process a particular target uses to generate code.
2. All of the gooee details of the sparc backend are now localized in the lib/CodeGen/TargetMAchine/Sparc directory.  The Sparc.h file that is globally visible is just a stub.
3. The Sparc.h file that esxists now will dissapear entirely someday when we have multiple backends chosen by a factory of some sort.

llvm-svn: 559
This commit is contained in:
Chris Lattner 2001-09-14 03:37:52 +00:00
parent ff0c8a7511
commit 0a823a062c
12 changed files with 1771 additions and 1798 deletions
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1683
llvm/include/llvm/CodeGen/Sparc.h
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File diff suppressed because it is too large Load Diff

31
llvm/include/llvm/CodeGen/TargetMachine.h
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@ -12,23 +12,14 @@
#ifndef LLVM_CODEGEN_TARGETMACHINE_H
#define LLVM_CODEGEN_TARGETMACHINE_H
//*********************** System Include Files *****************************/
#include "llvm/CodeGen/TargetData.h"
#include "llvm/Support/NonCopyable.h"
#include "llvm/Support/DataTypes.h"
#include <string>
#include <vector>
#include <hash_map>
#include <hash_set>
#include <algorithm>
//************************ User Include Files *****************************/
#include "llvm/CodeGen/TargetData.h"
#include "llvm/Support/NonCopyable.h"
#include "llvm/Support/DataTypes.h"
//************************ Opaque Declarations*****************************/
class Type;
class StructType;
struct MachineInstrDescriptor;
class TargetMachine;
@ -685,7 +676,6 @@ public:
//
//--------------------------------------------------------------------------
class Value;
class LiveRangeInfo;
class Method;
class Instruction;
@ -786,6 +776,19 @@ public:
const MachineRegInfo& getRegInfo() const { return *machineRegInfo; }
// compileMethod - This does everything neccesary to compile a method into the
// built in representation. This allows the target to have complete control
// over how it does compilation. This does not emit assembly or output
// machine code however, this is done later.
//
virtual bool compileMethod(Method *M) = 0;
// emitAssembly - Output assembly language code (a .s file) for the specified
// method. The specified method must have been compiled before this may be
// used.
//
virtual void emitAssembly(Method *M, ostream &OutStr) { /* todo */ }
protected:
// Description of machine instructions
// Protect so that subclass can control alloc/dealloc
@ -795,6 +798,4 @@ protected:
};
//**************************************************************************/
#endif

160
llvm/lib/CodeGen/InstrSelection/InstrSelection.cpp
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@ -45,10 +45,7 @@ cl::Enum<enum SelectDebugLevel_t> SelectDebugLevel("dselect", cl::NoFlags,
// Returns true if instruction selection failed, false otherwise.
//---------------------------------------------------------------------------
bool
SelectInstructionsForMethod(Method* method,
TargetMachine &Target)
{
bool SelectInstructionsForMethod(Method* method, TargetMachine &Target) {
bool failed = false;
//
@ -69,49 +66,42 @@ SelectInstructionsForMethod(Method* method,
//
const hash_set<InstructionNode*> &treeRoots = instrForest.getRootSet();
for (hash_set<InstructionNode*>::const_iterator
treeRootIter = treeRoots.begin();
treeRootIter != treeRoots.end();
++treeRootIter)
{
InstrTreeNode* basicNode = *treeRootIter;
treeRootIter = treeRoots.begin(); treeRootIter != treeRoots.end();
++treeRootIter) {
InstrTreeNode* basicNode = *treeRootIter;
// Invoke BURM to label each tree node with a state
(void) burm_label(basicNode);
// Invoke BURM to label each tree node with a state
burm_label(basicNode);
if (SelectDebugLevel >= Select_DebugBurgTrees)
{
printcover(basicNode, 1, 0);
cerr << "\nCover cost == " << treecost(basicNode, 1, 0) << "\n\n";
printMatches(basicNode);
}
// Then recursively walk the tree to select instructions
if (SelectInstructionsForTree(basicNode, /*goalnt*/1, Target))
{
failed = true;
break;
}
if (SelectDebugLevel >= Select_DebugBurgTrees) {
printcover(basicNode, 1, 0);
cerr << "\nCover cost == " << treecost(basicNode, 1, 0) << "\n\n";
printMatches(basicNode);
}
// Then recursively walk the tree to select instructions
if (SelectInstructionsForTree(basicNode, /*goalnt*/1, Target)) {
failed = true;
break;
}
}
//
// Record instructions in the vector for each basic block
//
for (Method::iterator BI = method->begin(); BI != method->end(); ++BI)
{
MachineCodeForBasicBlock& bbMvec = (*BI)->getMachineInstrVec();
for (BasicBlock::iterator II = (*BI)->begin(); II != (*BI)->end(); ++II)
{
MachineCodeForVMInstr& mvec = (*II)->getMachineInstrVec();
for (unsigned i=0; i < mvec.size(); i++)
bbMvec.push_back(mvec[i]);
}
for (Method::iterator BI = method->begin(); BI != method->end(); ++BI) {
MachineCodeForBasicBlock& bbMvec = (*BI)->getMachineInstrVec();
for (BasicBlock::iterator II = (*BI)->begin(); II != (*BI)->end(); ++II) {
MachineCodeForVMInstr& mvec = (*II)->getMachineInstrVec();
for (unsigned i=0; i < mvec.size(); i++)
bbMvec.push_back(mvec[i]);
}
}
if (SelectDebugLevel >= Select_PrintMachineCode)
{
cout << endl << "*** Machine instructions after INSTRUCTION SELECTION" << endl;
PrintMachineInstructions(method);
}
if (SelectDebugLevel >= Select_PrintMachineCode) {
cout << endl << "*** Machine instructions after INSTRUCTION SELECTION" << endl;
PrintMachineInstructions(method);
}
return false;
}
@ -177,10 +167,8 @@ FoldGetElemChain(const InstructionNode* getElemInstrNode,
// may be used by multiple instructions).
//---------------------------------------------------------------------------
bool
SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt,
TargetMachine &Target)
{
bool SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt,
TargetMachine &Target) {
// Use a static vector to avoid allocating a new one per VM instruction
static MachineInstr* minstrVec[MAX_INSTR_PER_VMINSTR];
@ -188,11 +176,10 @@ SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt,
//
int ruleForNode = burm_rule(treeRoot->state, goalnt);
if (ruleForNode == 0)
{
cerr << "Could not match instruction tree for instr selection" << endl;
return true;
}
if (ruleForNode == 0) {
cerr << "Could not match instruction tree for instr selection" << endl;
return true;
}
// Get this rule's non-terminals and the corresponding child nodes (if any)
//
@ -203,55 +190,48 @@ SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt,
// (If this is a list node, not an instruction, then skip this step).
// This function is specific to the target architecture.
//
if (treeRoot->opLabel != VRegListOp)
{
InstructionNode* instrNode = (InstructionNode*)treeRoot;
assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);
unsigned N = GetInstructionsByRule(instrNode, ruleForNode, nts, Target,
minstrVec);
assert(N <= MAX_INSTR_PER_VMINSTR);
for (unsigned i=0; i < N; i++)
{
assert(minstrVec[i] != NULL);
instrNode->getInstruction()->addMachineInstruction(minstrVec[i]);
}
if (treeRoot->opLabel != VRegListOp) {
InstructionNode* instrNode = (InstructionNode*)treeRoot;
assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);
unsigned N = GetInstructionsByRule(instrNode, ruleForNode, nts, Target,
minstrVec);
assert(N <= MAX_INSTR_PER_VMINSTR);
for (unsigned i=0; i < N; i++) {
assert(minstrVec[i] != NULL);
instrNode->getInstruction()->addMachineInstruction(minstrVec[i]);
}
}
// Then, recursively compile the child nodes, if any.
//
if (nts[0])
{ // i.e., there is at least one kid
InstrTreeNode* kids[2];
int currentRule = ruleForNode;
if (nts[0]) { // i.e., there is at least one kid
InstrTreeNode* kids[2];
int currentRule = ruleForNode;
burm_kids(treeRoot, currentRule, kids);
// First skip over any chain rules so that we don't visit
// the current node again.
//
while (ThisIsAChainRule(currentRule)) {
currentRule = burm_rule(treeRoot->state, nts[0]);
nts = burm_nts[currentRule];
burm_kids(treeRoot, currentRule, kids);
// First skip over any chain rules so that we don't visit
// the current node again.
//
while (ThisIsAChainRule(currentRule))
{
currentRule = burm_rule(treeRoot->state, nts[0]);
nts = burm_nts[currentRule];
burm_kids(treeRoot, currentRule, kids);
}
// Now we have the first non-chain rule so we have found
// the actual child nodes. Recursively compile them.
//
for (int i = 0; nts[i]; i++)
{
assert(i < 2);
InstrTreeNode::InstrTreeNodeType nodeType = kids[i]->getNodeType();
if (nodeType == InstrTreeNode::NTVRegListNode ||
nodeType == InstrTreeNode::NTInstructionNode)
{
if (SelectInstructionsForTree(kids[i], nts[i], Target))
return true; // failure
}
}
}
// Now we have the first non-chain rule so we have found
// the actual child nodes. Recursively compile them.
//
for (int i = 0; nts[i]; i++) {
assert(i < 2);
InstrTreeNode::InstrTreeNodeType nodeType = kids[i]->getNodeType();
if (nodeType == InstrTreeNode::NTVRegListNode ||
nodeType == InstrTreeNode::NTInstructionNode) {
if (SelectInstructionsForTree(kids[i], nts[i], Target))
return true; // failure
}
}
}
return false; // success
}

2
llvm/lib/CodeGen/RegAlloc/PhyRegAlloc.h
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@ -35,8 +35,6 @@
#define PHY_REG_ALLOC_H
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/Sparc.h"
#include "llvm/CodeGen/RegClass.h"
#include "llvm/CodeGen/LiveRangeInfo.h"
#include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"

1
llvm/lib/CodeGen/TargetMachine/Sparc/Sparc.burg
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@ -1,6 +1,7 @@
%{ // -*- C++ -*-
#include <stdio.h>
#include <llvm/CodeGen/InstrForest.h>
//#include <llvm/Analysis/InstForest.h>
typedef InstrTreeNode* NODEPTR_TYPE;
#define OP_LABEL(p) ((p)->opLabel)

3
llvm/lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp
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@ -1,4 +1,3 @@
// $Id$
//***************************************************************************
// File:
// SparcInstrSelection.cpp
@ -9,7 +8,7 @@
// 7/02/01 - Vikram Adve - Created
//**************************************************************************/
#include "llvm/CodeGen/Sparc.h"
#include "SparcInternals.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/InstrForest.h"
#include "llvm/CodeGen/InstrSelection.h"

1667
llvm/lib/CodeGen/TargetMachine/Sparc/SparcInternals.h Normal file
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File diff suppressed because it is too large Load Diff

3
llvm/lib/CodeGen/TargetMachine/Sparc/SparcRegInfo.cpp
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@ -1,7 +1,6 @@
#include "SparcInternals.h"
#include "llvm/CodeGen/IGNode.h"
#include "llvm/CodeGen/SparcRegInfo.h"
#include "llvm/CodeGen/Sparc.h"
//-----------------------------------------------------------------------------
// Int Register Class

0
llvm/include/llvm/CodeGen/SparcRegInfo.h → llvm/lib/CodeGen/TargetMachine/Sparc/SparcRegInfo.h
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2
llvm/tools/Makefile
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@ -1,5 +1,5 @@
LEVEL = ..
DIRS = as dis opt analyze lli llc
DIRS = llc as dis opt analyze lli llc
include $(LEVEL)/Makefile.common

2
llvm/tools/llc/Makefile
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@ -1,6 +1,6 @@
LEVEL = ../..
TOOLNAME = llc
USEDLIBS = sched select sparc target opt livevar bcreader vmcore asmwriter analysis support
USEDLIBS = sparc sched select sparc target opt livevar bcreader vmcore asmwriter analysis support
include $(LEVEL)/Makefile.common

15
llvm/tools/llc/llc.cpp
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@ -7,8 +7,6 @@
#include "llvm/Bytecode/Reader.h"
#include "llvm/Optimizations/Normalize.h"
#include "llvm/CodeGen/InstrSelection.h"
#include "llvm/CodeGen/InstrScheduling.h"
#include "llvm/CodeGen/Sparc.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Module.h"
@ -28,17 +26,7 @@ static bool CompileModule(Module *M, TargetMachine &Target) {
NormalizeMethod(Meth);
if (SelectInstructionsForMethod(Meth, Target)) {
cerr << "Instruction selection failed for method " << Meth->getName()
<< "\n\n";
return true;
}
if (ScheduleInstructionsWithSSA(Meth, Target)) {
cerr << "Instruction scheduling before allocation failed for method "
<< Meth->getName() << "\n\n";
return true;
}
if (Target.compileMethod(Meth)) return true;
}
return false;
@ -72,3 +60,4 @@ int main(int argc, char** argv) {
delete module;
return 0;
}