forked from OSchip/llvm-project
[X86] Don't mark SEXTLOAD v4i8->v4i64 and v8i8->v8i64 as custom under vector widening legalization.
This was tricking us into making these operations and then letting them get scalarized later. But I can't prove that the scalarized version is actually better. llvm-svn: 350141
This commit is contained in:
Craig Topper
parent
48615c1786
commit
0a6cec6f9f
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@ -897,14 +897,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::v8i8, Custom);
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}
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if (ExperimentalVectorWideningLegalization &&
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!Subtarget.hasSSE41() && Subtarget.is64Bit()) {
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// This lets DAG combine create sextloads that get split and scalarized.
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// TODO: Does this make sense? What about v2i8->v2i64?
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setLoadExtAction(ISD::SEXTLOAD, MVT::v4i64, MVT::v4i8, Custom);
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setLoadExtAction(ISD::SEXTLOAD, MVT::v8i64, MVT::v8i8, Custom);
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}
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for (auto VT : { MVT::v2f64, MVT::v2i64 }) {
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setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
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setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
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@ -1921,30 +1921,28 @@ entry:
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define <4 x i64> @load_sext_4i8_to_4i64(<4 x i8> *%ptr) {
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; SSE2-LABEL: load_sext_4i8_to_4i64:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: movsbq 1(%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm1
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; SSE2-NEXT: movsbq (%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm0
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: movsbq 3(%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm2
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; SSE2-NEXT: movsbq 2(%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm1
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
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; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
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; SSE2-NEXT: psrad $24, %xmm1
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; SSE2-NEXT: pxor %xmm2, %xmm2
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; SSE2-NEXT: pcmpgtd %xmm1, %xmm2
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; SSE2-NEXT: movdqa %xmm1, %xmm0
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_sext_4i8_to_4i64:
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; SSSE3: # %bb.0: # %entry
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; SSSE3-NEXT: movsbq 1(%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm1
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; SSSE3-NEXT: movsbq (%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm0
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSSE3-NEXT: movsbq 3(%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm2
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; SSSE3-NEXT: movsbq 2(%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm1
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
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; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
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; SSSE3-NEXT: psrad $24, %xmm1
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; SSSE3-NEXT: pxor %xmm2, %xmm2
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; SSSE3-NEXT: pcmpgtd %xmm1, %xmm2
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; SSSE3-NEXT: movdqa %xmm1, %xmm0
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; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
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; SSSE3-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_sext_4i8_to_4i64:
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@ -1999,20 +1997,24 @@ entry:
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define <2 x i64> @load_sext_4i8_to_4i64_extract(<4 x i8> *%ptr) {
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; SSE2-LABEL: load_sext_4i8_to_4i64_extract:
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; SSE2: # %bb.0:
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; SSE2-NEXT: movsbq 3(%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm1
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; SSE2-NEXT: movsbq 2(%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm0
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSE2-NEXT: psrad $24, %xmm0
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; SSE2-NEXT: pxor %xmm1, %xmm1
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; SSE2-NEXT: pcmpgtd %xmm0, %xmm1
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; SSE2-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_sext_4i8_to_4i64_extract:
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; SSSE3: # %bb.0:
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; SSSE3-NEXT: movsbq 3(%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm1
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; SSSE3-NEXT: movsbq 2(%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm0
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
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; SSSE3-NEXT: psrad $24, %xmm0
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; SSSE3-NEXT: pxor %xmm1, %xmm1
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; SSSE3-NEXT: pcmpgtd %xmm0, %xmm1
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; SSSE3-NEXT: punpckhdq {{.*#+}} xmm0 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_sext_4i8_to_4i64_extract:
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@ -2402,50 +2404,42 @@ entry:
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define <8 x i64> @load_sext_8i8_to_8i64(<8 x i8> *%ptr) {
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; SSE2-LABEL: load_sext_8i8_to_8i64:
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; SSE2: # %bb.0: # %entry
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; SSE2-NEXT: movsbq 1(%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm1
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; SSE2-NEXT: movsbq (%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm0
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSE2-NEXT: movsbq 3(%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm2
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; SSE2-NEXT: movsbq 2(%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm1
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
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; SSE2-NEXT: movsbq 5(%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm3
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; SSE2-NEXT: movsbq 4(%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm2
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
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; SSE2-NEXT: movsbq 7(%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm4
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; SSE2-NEXT: movsbq 6(%rdi), %rax
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; SSE2-NEXT: movq %rax, %xmm3
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; SSE2-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
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; SSE2-NEXT: movq {{.*#+}} xmm2 = mem[0],zero
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; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSE2-NEXT: psrad $24, %xmm1
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; SSE2-NEXT: pxor %xmm4, %xmm4
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; SSE2-NEXT: pxor %xmm3, %xmm3
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; SSE2-NEXT: pcmpgtd %xmm1, %xmm3
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; SSE2-NEXT: movdqa %xmm1, %xmm0
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; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
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; SSE2-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
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; SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
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; SSE2-NEXT: psrad $24, %xmm3
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; SSE2-NEXT: pcmpgtd %xmm3, %xmm4
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; SSE2-NEXT: movdqa %xmm3, %xmm2
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; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
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; SSE2-NEXT: punpckhdq {{.*#+}} xmm3 = xmm3[2],xmm4[2],xmm3[3],xmm4[3]
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; SSE2-NEXT: retq
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;
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; SSSE3-LABEL: load_sext_8i8_to_8i64:
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; SSSE3: # %bb.0: # %entry
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; SSSE3-NEXT: movsbq 1(%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm1
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; SSSE3-NEXT: movsbq (%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm0
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
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; SSSE3-NEXT: movsbq 3(%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm2
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; SSSE3-NEXT: movsbq 2(%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm1
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
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; SSSE3-NEXT: movsbq 5(%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm3
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; SSSE3-NEXT: movsbq 4(%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm2
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
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; SSSE3-NEXT: movsbq 7(%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm4
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; SSSE3-NEXT: movsbq 6(%rdi), %rax
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; SSSE3-NEXT: movq %rax, %xmm3
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; SSSE3-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm4[0]
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; SSSE3-NEXT: movq {{.*#+}} xmm2 = mem[0],zero
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; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
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; SSSE3-NEXT: psrad $24, %xmm1
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; SSSE3-NEXT: pxor %xmm4, %xmm4
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; SSSE3-NEXT: pxor %xmm3, %xmm3
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; SSSE3-NEXT: pcmpgtd %xmm1, %xmm3
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; SSSE3-NEXT: movdqa %xmm1, %xmm0
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; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
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; SSSE3-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
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; SSSE3-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
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; SSSE3-NEXT: psrad $24, %xmm3
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; SSSE3-NEXT: pcmpgtd %xmm3, %xmm4
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; SSSE3-NEXT: movdqa %xmm3, %xmm2
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; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
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; SSSE3-NEXT: punpckhdq {{.*#+}} xmm3 = xmm3[2],xmm4[2],xmm3[3],xmm4[3]
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; SSSE3-NEXT: retq
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;
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; SSE41-LABEL: load_sext_8i8_to_8i64:
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