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AMDGPU: Do not re-use tmpreg in spill/restore lowering 

The register scavenging code does not support multiple definitions of
the same vreg.

Differential Revision: https://reviews.llvm.org/D25220

llvm-svn: 283369
This commit is contained in:
Matthias Braun 2016-10-05 20:02:51 +00:00
parent 386546124f
commit 0a6916f303
1 changed files with 2 additions and 2 deletions
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4
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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@ -417,13 +417,13 @@ void SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
const DebugLoc &DL = MI->getDebugLoc();
unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
unsigned SuperReg = MI->getOperand(0).getReg();
bool IsKill = MI->getOperand(0).isKill();
// SubReg carries the "Kill" flag when SubReg == SuperReg.
unsigned SubKillState = getKillRegState((NumSubRegs == 1) && IsKill);
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
unsigned SubReg = NumSubRegs == 1 ?
SuperReg : getSubReg(SuperReg, getSubRegFromChannel(i));
@ -503,7 +503,6 @@ void SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
const DebugLoc &DL = MI->getDebugLoc();
unsigned NumSubRegs = getNumSubRegsForSpillOp(MI->getOpcode());
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
unsigned SuperReg = MI->getOperand(0).getReg();
// m0 is not allowed as with readlane/writelane, so a temporary SGPR and
@ -515,6 +514,7 @@ void SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
}
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
unsigned SubReg = NumSubRegs == 1 ?
SuperReg : getSubReg(SuperReg, getSubRegFromChannel(i));