maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[RISCV] Fix disassembling of fence instruction with invalid field 

Summary:
Instruction with 0 in fence field being disassembled as fence , iorw.
Printing "unknown" to match GAS behavior.

This bug was uncovered by a LLVM MC Disassembler Protocol Buffer Fuzzer
for the RISC-V assembly language.

Reviewers: asb

Subscribers: rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, asb

Differential Revision: https://reviews.llvm.org/D51828

llvm-svn: 344309
This commit is contained in:
Ana Pazos 2018-10-11 22:49:13 +00:00
parent dfd1760b5f
commit 0a5fcefa31
3 changed files with 14 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
View File

@ -93,6 +93,8 @@ void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, const MCSubtargetInfo &STI,
raw_ostream &O) { raw_ostream &O) {
unsigned FenceArg = MI->getOperand(OpNo).getImm(); unsigned FenceArg = MI->getOperand(OpNo).getImm();
assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
if ((FenceArg & RISCVFenceField::I) != 0) if ((FenceArg & RISCVFenceField::I) != 0)
O << 'i'; O << 'i';
if ((FenceArg & RISCVFenceField::O) != 0) if ((FenceArg & RISCVFenceField::O) != 0)
@ -101,6 +103,8 @@ void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
O << 'r'; O << 'r';
if ((FenceArg & RISCVFenceField::W) != 0) if ((FenceArg & RISCVFenceField::W) != 0)
O << 'w'; O << 'w';
if (FenceArg == 0)
O << "unknown";
} }
void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo, void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,

9
llvm/test/MC/Disassembler/RISCV/unknown-fence-field.txt Normal file
View File

@ -0,0 +1,9 @@
# RUN: llvm-mc -disassemble -triple=riscv32 < %s 2>&1 | FileCheck %s
# RUN: llvm-mc -disassemble -triple=riscv64 < %s 2>&1 | FileCheck %s
#
# Test generated by a LLVM MC Disassembler Protocol Buffer Fuzzer
# for the RISC-V assembly language.
# This decodes as fence , iorw with invalid fence field as 0.
[0x0f 0x00 0xf0 0x00]
# CHECK: fence unknown, iorw

1
llvm/test/MC/RISCV/rv32i-invalid.s
View File

@ -6,6 +6,7 @@ fence iorw, iore # CHECK: :[[@LINE]]:13: error: operand must be formed of letter
fence wr, wr # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw' fence wr, wr # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw'
fence rw, rr # CHECK: :[[@LINE]]:11: error: operand must be formed of letters selected in-order from 'iorw' fence rw, rr # CHECK: :[[@LINE]]:11: error: operand must be formed of letters selected in-order from 'iorw'
fence 1, rw # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw' fence 1, rw # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw'
fence unknown, unknown # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw'
## uimm5 ## uimm5
slli a0, a0, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] slli a0, a0, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]