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AMDGPU: Allow specifying different opcode on VI for SMRD/SMEM 

Although the basic s_load_* instructions happen to use the same
opcode, some of the special case SMRD instructions have
different opcodes.

llvm-svn: 245775
This commit is contained in:
Matt Arsenault 2015-08-22 00:54:31 +00:00
parent e8df879948
commit 0a3ac1be43
2 changed files with 21 additions and 15 deletions
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16
llvm/lib/Target/AMDGPU/SIInstrInfo.td
View File

@ -72,6 +72,12 @@ class sopk <bits<5> si, bits<5> vi = si> {
field bits<5> VI = vi;
}
// Specify an SMRD opcode for SI and SMEM opcode for VI
class smrd<bits<5> si, bits<5> vi = si> {
field bits<5> SI = si;
field bits<8> VI = { 0, 0, 0, vi };
}
// Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
// in AMDGPUInstrInfo.cpp
def SISubtarget {
@ -900,21 +906,21 @@ class SMRD_Real_vi <bits<8> op, string opName, bit imm, dag outs, dag ins,
let AssemblerPredicates = [isVI];
}
multiclass SMRD_m <bits<5> op, string opName, bit imm, dag outs, dag ins,
multiclass SMRD_m <smrd op, string opName, bit imm, dag outs, dag ins,
string asm, list<dag> pattern> {
def "" : SMRD_Pseudo <opName, outs, ins, pattern>;
def _si : SMRD_Real_si <op, opName, imm, outs, ins, asm>;
def _si : SMRD_Real_si <op.SI, opName, imm, outs, ins, asm>;
// glc is only applicable to scalar stores, which are not yet
// implemented.
let glc = 0 in {
def _vi : SMRD_Real_vi <{0, 0, 0, op}, opName, imm, outs, ins, asm>;
def _vi : SMRD_Real_vi <op.VI, opName, imm, outs, ins, asm>;
}
}
multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
multiclass SMRD_Helper <smrd op, string opName, RegisterClass baseClass,
RegisterClass dstClass> {
defm _IMM : SMRD_m <
op, opName#"_IMM", 1, (outs dstClass:$dst),
@ -924,7 +930,7 @@ multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
def _IMM_ci : SMRD <
(outs dstClass:$dst), (ins baseClass:$sbase, smrd_literal_offset:$offset),
opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op> {
opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op.SI> {
let AssemblerPredicates = [isCIOnly];
}

20
llvm/lib/Target/AMDGPU/SIInstructions.td
View File

@ -62,30 +62,30 @@ let mayLoad = 1 in {
// We are using the SGPR_32 and not the SReg_32 register class for 32-bit
// SMRD instructions, because the SGPR_32 register class does not include M0
// and writing to M0 from an SMRD instruction will hang the GPU.
defm S_LOAD_DWORD : SMRD_Helper <0x00, "s_load_dword", SReg_64, SGPR_32>;
defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "s_load_dwordx2", SReg_64, SReg_64>;
defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "s_load_dwordx4", SReg_64, SReg_128>;
defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "s_load_dwordx8", SReg_64, SReg_256>;
defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "s_load_dwordx16", SReg_64, SReg_512>;
defm S_LOAD_DWORD : SMRD_Helper <smrd<0x00>, "s_load_dword", SReg_64, SGPR_32>;
defm S_LOAD_DWORDX2 : SMRD_Helper <smrd<0x01>, "s_load_dwordx2", SReg_64, SReg_64>;
defm S_LOAD_DWORDX4 : SMRD_Helper <smrd<0x02>, "s_load_dwordx4", SReg_64, SReg_128>;
defm S_LOAD_DWORDX8 : SMRD_Helper <smrd<0x03>, "s_load_dwordx8", SReg_64, SReg_256>;
defm S_LOAD_DWORDX16 : SMRD_Helper <smrd<0x04>, "s_load_dwordx16", SReg_64, SReg_512>;
defm S_BUFFER_LOAD_DWORD : SMRD_Helper <
0x08, "s_buffer_load_dword", SReg_128, SGPR_32
smrd<0x08>, "s_buffer_load_dword", SReg_128, SGPR_32
>;
defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper <
0x09, "s_buffer_load_dwordx2", SReg_128, SReg_64
smrd<0x09>, "s_buffer_load_dwordx2", SReg_128, SReg_64
>;
defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper <
0x0a, "s_buffer_load_dwordx4", SReg_128, SReg_128
smrd<0x0a>, "s_buffer_load_dwordx4", SReg_128, SReg_128
>;
defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper <
0x0b, "s_buffer_load_dwordx8", SReg_128, SReg_256
smrd<0x0b>, "s_buffer_load_dwordx8", SReg_128, SReg_256
>;
defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper <
0x0c, "s_buffer_load_dwordx16", SReg_128, SReg_512
smrd<0x0c>, "s_buffer_load_dwordx16", SReg_128, SReg_512
>;
} // mayLoad = 1