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[RISCV] Don't allow vector types to be used with inline asm 'r' constraint 

The 'r' constraint uses the GPR class. There is generic support
for bitcasting and extending/truncating non-integer VTs to the
required integer VT. This doesn't work for scalable vectors and
instead crashes.

To prevent this, explicitly reject vectors. Fixed vectors might
work without crashing, but it doesn't seem worthwhile to allow.

While there remove an unnecessary level of indentation in the
"vr" and "vm" constraint handling.

Differential Revision: https://reviews.llvm.org/D115810
This commit is contained in:
Craig Topper 2021-12-23 15:20:06 -06:00
parent 1abbbc7b24
commit 0a35211b34
2 changed files with 23 additions and 10 deletions
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21
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
View File

@ -9657,6 +9657,9 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
if (Constraint.size() == 1) {
switch (Constraint[0]) {
case 'r':
// TODO: Support fixed vectors up to XLen for P extension?
if (VT.isVector())
break;
return std::make_pair(0U, &RISCV::GPRRegClass);
case 'f':
if (Subtarget.hasStdExtZfh() && VT == MVT::f16)
@ -9669,17 +9672,15 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
default:
break;
}
} else {
if (Constraint == "vr") {
for (const auto *RC : {&RISCV::VRRegClass, &RISCV::VRM2RegClass,
&RISCV::VRM4RegClass, &RISCV::VRM8RegClass}) {
if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
return std::make_pair(0U, RC);
}
} else if (Constraint == "vm") {
if (TRI->isTypeLegalForClass(RISCV::VMV0RegClass, VT.SimpleTy))
return std::make_pair(0U, &RISCV::VMV0RegClass);
} else if (Constraint == "vr") {
for (const auto *RC : {&RISCV::VRRegClass, &RISCV::VRM2RegClass,
&RISCV::VRM4RegClass, &RISCV::VRM8RegClass}) {
if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
return std::make_pair(0U, RC);
}
} else if (Constraint == "vm") {
if (TRI->isTypeLegalForClass(RISCV::VMV0RegClass, VT.SimpleTy))
return std::make_pair(0U, &RISCV::VMV0RegClass);
}
// Clang will correctly decode the usage of register name aliases into their

12
llvm/test/CodeGen/RISCV/inline-asm-invalid.ll
View File

@ -30,3 +30,15 @@ define void @constraint_f() nounwind {
tail call void asm "fadd.d fa0, fa0, $0", "f"(double 0.0)
ret void
}
define void @constraint_r_fixed_vec() nounwind {
; CHECK: error: couldn't allocate input reg for constraint 'r'
tail call void asm "add a0, a0, $0", "r"(<4 x i32> zeroinitializer)
ret void
}
define void @constraint_r_scalable_vec() nounwind {
; CHECK: error: couldn't allocate input reg for constraint 'r'
tail call void asm "add a0, a0, $0", "r"(<vscale x 4 x i32> zeroinitializer)
ret void
}