forked from OSchip/llvm-project
[MIPS GlobalISel] Select fabs
Select G_FABS for MIPS32. Differential Revision: https://reviews.llvm.org/D62903 llvm-svn: 362690
This commit is contained in:
Petar Avramovic
parent
a7d0006447
commit
0a1fd355b2
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@ -357,6 +357,16 @@ bool MipsInstructionSelector::select(MachineInstr &I,
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I.eraseFromParent();
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return true;
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}
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case G_FABS: {
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unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
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unsigned FABSOpcode =
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Size == 32 ? Mips::FABS_S
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: STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32;
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MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(FABSOpcode))
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.add(I.getOperand(0))
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.add(I.getOperand(1));
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break;
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}
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case G_GLOBAL_VALUE: {
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const llvm::GlobalValue *GVal = I.getOperand(1).getGlobal();
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if (MF.getTarget().isPositionIndependent()) {
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@ -94,7 +94,7 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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getActionDefinitionsBuilder(G_FCONSTANT)
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.legalFor({s32, s64});
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getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
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getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FABS})
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.legalFor({s32, s64});
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getActionDefinitionsBuilder(G_FCMP)
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@ -133,7 +133,8 @@ MipsRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
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case G_FADD:
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case G_FSUB:
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case G_FMUL:
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case G_FDIV: {
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case G_FDIV:
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case G_FABS: {
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unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
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assert((Size == 32 || Size == 64) && "Unsupported floating point size");
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OperandsMapping = Size == 32 ? &Mips::ValueMappings[Mips::SPRIdx]
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@ -0,0 +1,65 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
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--- |
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define void @fabs_f32() {entry: ret void}
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define void @fabs_f64() {entry: ret void}
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...
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---
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name: fabs_f32
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12
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; FP32-LABEL: name: fabs_f32
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; FP32: liveins: $f12
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; FP32: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP32: [[FABS_S:%[0-9]+]]:fgr32 = FABS_S [[COPY]]
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; FP32: $f0 = COPY [[FABS_S]]
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: fabs_f32
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; FP64: liveins: $f12
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; FP64: [[COPY:%[0-9]+]]:fgr32 = COPY $f12
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; FP64: [[FABS_S:%[0-9]+]]:fgr32 = FABS_S [[COPY]]
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; FP64: $f0 = COPY [[FABS_S]]
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; FP64: RetRA implicit $f0
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%0:fprb(s32) = COPY $f12
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%1:fprb(s32) = G_FABS %0
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$f0 = COPY %1(s32)
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RetRA implicit $f0
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...
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---
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name: fabs_f64
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alignment: 2
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6
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; FP32-LABEL: name: fabs_f64
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; FP32: liveins: $d6
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; FP32: [[COPY:%[0-9]+]]:afgr64 = COPY $d6
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; FP32: [[FABS_D32_:%[0-9]+]]:afgr64 = FABS_D32 [[COPY]]
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; FP32: $d0 = COPY [[FABS_D32_]]
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: fabs_f64
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; FP64: liveins: $d6
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; FP64: [[COPY:%[0-9]+]]:fgr64 = COPY $d6
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; FP64: [[FABS_D64_:%[0-9]+]]:fgr64 = FABS_D64 [[COPY]]
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; FP64: $d0 = COPY [[FABS_D64_]]
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; FP64: RetRA implicit $d0
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%0:fprb(s64) = COPY $d6
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%1:fprb(s64) = G_FABS %0
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$d0 = COPY %1(s64)
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RetRA implicit $d0
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...
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@ -0,0 +1,61 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
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--- |
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define void @fabs_f32() {entry: ret void}
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define void @fabs_f64() {entry: ret void}
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...
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---
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name: fabs_f32
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12
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; FP32-LABEL: name: fabs_f32
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; FP32: liveins: $f12
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; FP32: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP32: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
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; FP32: $f0 = COPY [[FABS]](s32)
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: fabs_f32
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; FP64: liveins: $f12
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; FP64: [[COPY:%[0-9]+]]:_(s32) = COPY $f12
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; FP64: [[FABS:%[0-9]+]]:_(s32) = G_FABS [[COPY]]
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; FP64: $f0 = COPY [[FABS]](s32)
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; FP64: RetRA implicit $f0
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%0:_(s32) = COPY $f12
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%1:_(s32) = G_FABS %0
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$f0 = COPY %1(s32)
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RetRA implicit $f0
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...
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---
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name: fabs_f64
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6
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; FP32-LABEL: name: fabs_f64
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; FP32: liveins: $d6
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; FP32: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
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; FP32: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
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; FP32: $d0 = COPY [[FABS]](s64)
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: fabs_f64
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; FP64: liveins: $d6
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; FP64: [[COPY:%[0-9]+]]:_(s64) = COPY $d6
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; FP64: [[FABS:%[0-9]+]]:_(s64) = G_FABS [[COPY]]
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; FP64: $d0 = COPY [[FABS]](s64)
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; FP64: RetRA implicit $d0
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%0:_(s64) = COPY $d6
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%1:_(s64) = G_FABS %0
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$d0 = COPY %1(s64)
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RetRA implicit $d0
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...
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@ -0,0 +1,27 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP32
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32,FP64
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declare float @llvm.fabs.f32(float)
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define float @fabs_f32(float %a) {
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; MIPS32-LABEL: fabs_f32:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: abs.s $f0, $f12
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%0 = call float @llvm.fabs.f32(float %a)
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ret float %0
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}
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declare double @llvm.fabs.f64(double)
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define double @fabs_f64(double %a) {
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; MIPS32-LABEL: fabs_f64:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: abs.d $f0, $f12
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%0 = call double @llvm.fabs.f64(double %a)
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ret double %0
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}
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@ -0,0 +1,63 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP32
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -mattr=+fp64,+mips32r2 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=FP64
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--- |
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define void @fabs_f32() {entry: ret void}
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define void @fabs_f64() {entry: ret void}
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...
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---
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name: fabs_f32
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $f12
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; FP32-LABEL: name: fabs_f32
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; FP32: liveins: $f12
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; FP32: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
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; FP32: [[FABS:%[0-9]+]]:fprb(s32) = G_FABS [[COPY]]
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; FP32: $f0 = COPY [[FABS]](s32)
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; FP32: RetRA implicit $f0
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; FP64-LABEL: name: fabs_f32
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; FP64: liveins: $f12
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; FP64: [[COPY:%[0-9]+]]:fprb(s32) = COPY $f12
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; FP64: [[FABS:%[0-9]+]]:fprb(s32) = G_FABS [[COPY]]
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; FP64: $f0 = COPY [[FABS]](s32)
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; FP64: RetRA implicit $f0
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%0:_(s32) = COPY $f12
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%1:_(s32) = G_FABS %0
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$f0 = COPY %1(s32)
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RetRA implicit $f0
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...
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---
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name: fabs_f64
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $d6
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; FP32-LABEL: name: fabs_f64
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; FP32: liveins: $d6
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; FP32: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
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; FP32: [[FABS:%[0-9]+]]:fprb(s64) = G_FABS [[COPY]]
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; FP32: $d0 = COPY [[FABS]](s64)
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; FP32: RetRA implicit $d0
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; FP64-LABEL: name: fabs_f64
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; FP64: liveins: $d6
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; FP64: [[COPY:%[0-9]+]]:fprb(s64) = COPY $d6
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; FP64: [[FABS:%[0-9]+]]:fprb(s64) = G_FABS [[COPY]]
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; FP64: $d0 = COPY [[FABS]](s64)
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; FP64: RetRA implicit $d0
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%0:_(s64) = COPY $d6
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%1:_(s64) = G_FABS %0
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$d0 = COPY %1(s64)
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RetRA implicit $d0
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...
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