forked from OSchip/llvm-project
[Mips] Implement hasDivRemOp()
SDIVREM and UDIVREM can be customized lowered in MipsSE. Fix https://github.com/llvm/llvm-project/issues/54991. Reviewed By: sdardis Differential Revision: https://reviews.llvm.org/D124980
This commit is contained in:
Jim Lin
parent
49b0c60542
commit
0a0d6489ef
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@ -61,6 +61,7 @@ add_llvm_target(MipsCodeGen
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MipsSubtarget.cpp
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MipsTargetMachine.cpp
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MipsTargetObjectFile.cpp
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MipsTargetTransformInfo.cpp
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MicroMipsSizeReduction.cpp
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MipsMulMulBugPass.cpp
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@ -18,6 +18,7 @@
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#include "MipsSEISelDAGToDAG.h"
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#include "MipsSubtarget.h"
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#include "MipsTargetObjectFile.h"
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#include "MipsTargetTransformInfo.h"
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#include "TargetInfo/MipsTargetInfo.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/ADT/STLExtras.h"
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@ -287,7 +288,7 @@ MipsTargetMachine::getTargetTransformInfo(const Function &F) const {
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}
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LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n");
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return TargetTransformInfo(BasicTTIImpl(this, F));
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return TargetTransformInfo(MipsTTIImpl(this, F));
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}
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// Implemented by targets that want to run passes immediately before
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@ -0,0 +1,17 @@
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//===-- MipsTargetTransformInfo.cpp - Mips specific TTI ----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "MipsTargetTransformInfo.h"
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using namespace llvm;
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bool MipsTTIImpl::hasDivRemOp(Type *DataType, bool IsSigned) {
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EVT VT = TLI->getValueType(DL, DataType);
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return TLI->isOperationLegalOrCustom(IsSigned ? ISD::SDIVREM : ISD::UDIVREM,
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VT);
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}
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@ -0,0 +1,40 @@
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//===-- MipsTargetTransformInfo.h - Mips specific TTI -----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_MIPS_MIPSTARGETTRANSFORMINFO_H
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#include "MipsTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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namespace llvm {
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class MipsTTIImpl : public BasicTTIImplBase<MipsTTIImpl> {
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using BaseT = BasicTTIImplBase<MipsTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const MipsSubtarget *ST;
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const MipsTargetLowering *TLI;
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const MipsSubtarget *getST() const { return ST; }
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const MipsTargetLowering *getTLI() const { return TLI; }
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public:
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explicit MipsTTIImpl(const MipsTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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bool hasDivRemOp(Type *DataType, bool IsSigned);
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};
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} // end namespace llvm
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#endif
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@ -7,8 +7,8 @@ define void @decompose_illegal_srem_same_block(i32 %a, i32 %b) {
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; CHECK-LABEL: @decompose_illegal_srem_same_block(
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[T0:%.*]] = mul i32 [[DIV]], [[B]]
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; CHECK-NEXT: [[REM:%.*]] = sub i32 [[A]], [[T0]]
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; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
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; CHECK-NEXT: [[REM_RECOMPOSED:%.*]] = srem i32 [[A]], [[B]]
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; CHECK-NEXT: call void @foo(i32 [[REM_RECOMPOSED]], i32 [[DIV]])
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; CHECK-NEXT: ret void
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;
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%div = sdiv i32 %a, %b
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@ -22,8 +22,8 @@ define void @decompose_illegal_urem_same_block(i32 %a, i32 %b) {
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; CHECK-LABEL: @decompose_illegal_urem_same_block(
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; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[T0:%.*]] = mul i32 [[DIV]], [[B]]
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; CHECK-NEXT: [[REM:%.*]] = sub i32 [[A]], [[T0]]
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; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
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; CHECK-NEXT: [[REM_RECOMPOSED:%.*]] = urem i32 [[A]], [[B]]
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; CHECK-NEXT: call void @foo(i32 [[REM_RECOMPOSED]], i32 [[DIV]])
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; CHECK-NEXT: ret void
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;
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%div = udiv i32 %a, %b
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@ -100,18 +100,13 @@ end:
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define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_unexpanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[X_FROZEN:%.*]] = freeze i32 [[X:%.*]]
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; CHECK-NEXT: [[T0_FROZEN:%.*]] = freeze i32 [[T0]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X_FROZEN]], [[T0_FROZEN]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[T1]], [[T0_FROZEN]]
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; CHECK-NEXT: [[T3_DECOMPOSED:%.*]] = sub i32 [[X_FROZEN]], [[TMP1]]
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; CHECK-NEXT: [[Y_FROZEN:%.*]] = freeze i32 [[Y]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_DECOMPOSED]], [[Y_FROZEN]]
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; CHECK-NEXT: [[T3:%.*]] = srem i32 [[X]], [[T0]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[T4]], [[Y_FROZEN]]
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; CHECK-NEXT: [[T6_DECOMPOSED:%.*]] = sub i32 [[T3_DECOMPOSED]], [[TMP2]]
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; CHECK-NEXT: ret i32 [[T6_DECOMPOSED]]
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; CHECK-NEXT: [[T6:%.*]] = srem i32 [[T3]], [[Y]]
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; CHECK-NEXT: ret i32 [[T6]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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@ -127,11 +122,11 @@ define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
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; CHECK-NEXT: [[T3_RECOMPOSED:%.*]] = srem i32 [[X]], [[T0]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]]
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; CHECK-NEXT: ret i32 [[T6]]
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; CHECK-NEXT: [[T6_RECOMPOSED:%.*]] = srem i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: ret i32 [[T6_RECOMPOSED]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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@ -5,12 +5,9 @@ declare void @foo(i32, i32)
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define void @decompose_illegal_srem_same_block(i32 %a, i32 %b) {
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; CHECK-LABEL: @decompose_illegal_srem_same_block(
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; CHECK-NEXT: [[A_FROZEN:%.*]] = freeze i32 [[A:%.*]]
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; CHECK-NEXT: [[B_FROZEN:%.*]] = freeze i32 [[B:%.*]]
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A_FROZEN]], [[B_FROZEN]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[B_FROZEN]]
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; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[A_FROZEN]], [[TMP1]]
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; CHECK-NEXT: call void @foo(i32 [[REM_DECOMPOSED]], i32 [[DIV]])
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; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A]], [[B]]
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; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
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; CHECK-NEXT: ret void
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;
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%rem = srem i32 %a, %b
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@ -21,12 +18,9 @@ define void @decompose_illegal_srem_same_block(i32 %a, i32 %b) {
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define void @decompose_illegal_urem_same_block(i32 %a, i32 %b) {
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; CHECK-LABEL: @decompose_illegal_urem_same_block(
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; CHECK-NEXT: [[A_FROZEN:%.*]] = freeze i32 [[A:%.*]]
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; CHECK-NEXT: [[B_FROZEN:%.*]] = freeze i32 [[B:%.*]]
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; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[A_FROZEN]], [[B_FROZEN]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[DIV]], [[B_FROZEN]]
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; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[A_FROZEN]], [[TMP1]]
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; CHECK-NEXT: call void @foo(i32 [[REM_DECOMPOSED]], i32 [[DIV]])
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; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[REM:%.*]] = urem i32 [[A]], [[B]]
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; CHECK-NEXT: call void @foo(i32 [[REM]], i32 [[DIV]])
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; CHECK-NEXT: ret void
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;
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%div = udiv i32 %a, %b
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@ -41,12 +35,9 @@ define void @decompose_illegal_urem_same_block(i32 %a, i32 %b) {
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define i32 @hoist_sdiv(i32 %a, i32 %b) {
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; CHECK-LABEL: @hoist_sdiv(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A_FROZEN:%.*]] = freeze i32 [[A:%.*]]
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; CHECK-NEXT: [[B_FROZEN:%.*]] = freeze i32 [[B:%.*]]
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A_FROZEN]], [[B_FROZEN]]
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; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[DIV]], [[B_FROZEN]]
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; CHECK-NEXT: [[REM_DECOMPOSED:%.*]] = sub i32 [[A_FROZEN]], [[TMP0]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM_DECOMPOSED]], 42
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; CHECK-NEXT: [[REM:%.*]] = srem i32 [[A:%.*]], [[B:%.*]]
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; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[A]], [[B]]
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[REM]], 42
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; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]]
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; CHECK: if:
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; CHECK-NEXT: br label [[END]]
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@ -169,18 +160,13 @@ end:
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define i32 @srem_of_srem_unexpanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-LABEL: @srem_of_srem_unexpanded(
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[X_FROZEN:%.*]] = freeze i32 [[X:%.*]]
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; CHECK-NEXT: [[T0_FROZEN:%.*]] = freeze i32 [[T0]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X_FROZEN]], [[T0_FROZEN]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[T1]], [[T0_FROZEN]]
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; CHECK-NEXT: [[T3_DECOMPOSED:%.*]] = sub i32 [[X_FROZEN]], [[TMP1]]
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; CHECK-NEXT: [[Y_FROZEN:%.*]] = freeze i32 [[Y]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_DECOMPOSED]], [[Y_FROZEN]]
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; CHECK-NEXT: [[T3:%.*]] = srem i32 [[X]], [[T0]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[TMP2:%.*]] = mul i32 [[T4]], [[Y_FROZEN]]
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; CHECK-NEXT: [[T6_DECOMPOSED:%.*]] = sub i32 [[T3_DECOMPOSED]], [[TMP2]]
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; CHECK-NEXT: ret i32 [[T6_DECOMPOSED]]
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; CHECK-NEXT: [[T6:%.*]] = srem i32 [[T3]], [[Y]]
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; CHECK-NEXT: ret i32 [[T6]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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@ -196,11 +182,11 @@ define i32 @srem_of_srem_expanded(i32 %X, i32 %Y, i32 %Z) {
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; CHECK-NEXT: [[T0:%.*]] = mul nsw i32 [[Z:%.*]], [[Y:%.*]]
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; CHECK-NEXT: [[T1:%.*]] = sdiv i32 [[X:%.*]], [[T0]]
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; CHECK-NEXT: [[T2:%.*]] = mul nsw i32 [[T0]], [[T1]]
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; CHECK-NEXT: [[T3:%.*]] = sub nsw i32 [[X]], [[T2]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3]], [[Y]]
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; CHECK-NEXT: [[T3_RECOMPOSED:%.*]] = srem i32 [[X]], [[T0]]
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; CHECK-NEXT: [[T4:%.*]] = sdiv i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: [[T5:%.*]] = mul nsw i32 [[T4]], [[Y]]
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; CHECK-NEXT: [[T6:%.*]] = sub nsw i32 [[T3]], [[T5]]
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; CHECK-NEXT: ret i32 [[T6]]
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; CHECK-NEXT: [[T6_RECOMPOSED:%.*]] = srem i32 [[T3_RECOMPOSED]], [[Y]]
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; CHECK-NEXT: ret i32 [[T6_RECOMPOSED]]
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;
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%t0 = mul nsw i32 %Z, %Y
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%t1 = sdiv i32 %X, %t0
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