forked from OSchip/llvm-project
[Power9]Legalize and emit code for quad-precision fma instructions
Legalize and emit code for the following quad-precision fma: * xsmaddqp * xsnmaddqp * xsmsubqp * xsnmsubqp Differential Revision: https://reviews.llvm.org/D44843 llvm-svn: 329206
This commit is contained in:
Lei Huang
parent
fb6a4a7907
commit
09fda63af0
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@ -798,6 +798,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
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setOperationAction(ISD::FMUL, MVT::f128, Legal);
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setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
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setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
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setOperationAction(ISD::FMA, MVT::f128, Legal);
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}
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}
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@ -13752,6 +13753,8 @@ bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
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case MVT::f32:
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case MVT::f64:
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return true;
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case MVT::f128:
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return (EnableQuadPrecision && Subtarget.hasP9Vector());
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default:
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break;
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}
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@ -2382,6 +2382,18 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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list<dag> pattern>
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: X_VT5_VA5_VB5<opcode, xo, opc, pattern>, isDOT;
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// [PO VRT VRA VRB XO /]
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class X_VT5_VA5_VB5_FMA<bits<6> opcode, bits<10> xo, string opc,
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list<dag> pattern>
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: XForm_1<opcode, xo, (outs vrrc:$vT), (ins vrrc:$vTi, vrrc:$vA, vrrc:$vB),
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!strconcat(opc, " $vT, $vA, $vB"), IIC_VecFP, pattern>,
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RegConstraint<"$vTi = $vT">, NoEncode<"$vTi">;
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// [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
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class X_VT5_VA5_VB5_FMA_Ro<bits<6> opcode, bits<10> xo, string opc,
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list<dag> pattern>
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: X_VT5_VA5_VB5_FMA<opcode, xo, opc, pattern>, isDOT;
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//===--------------------------------------------------------------------===//
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// Quad-Precision Scalar Move Instructions:
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@ -2424,14 +2436,30 @@ let AddedComplexity = 400, Predicates = [HasP9Vector] in {
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def XSSQRTQPO : X_VT5_XO5_VB5_Ro<63, 27, 804, "xssqrtqpo", []>;
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// (Negative) Multiply-{Add/Subtract}
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def XSMADDQP : X_VT5_VA5_VB5 <63, 388, "xsmaddqp" , []>;
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def XSMADDQPO : X_VT5_VA5_VB5_Ro<63, 388, "xsmaddqpo" , []>;
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def XSMSUBQP : X_VT5_VA5_VB5 <63, 420, "xsmsubqp" , []>;
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def XSMSUBQPO : X_VT5_VA5_VB5_Ro<63, 420, "xsmsubqpo" , []>;
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def XSNMADDQP : X_VT5_VA5_VB5 <63, 452, "xsnmaddqp" , []>;
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def XSNMADDQPO: X_VT5_VA5_VB5_Ro<63, 452, "xsnmaddqpo", []>;
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def XSNMSUBQP : X_VT5_VA5_VB5 <63, 484, "xsnmsubqp" , []>;
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def XSNMSUBQPO: X_VT5_VA5_VB5_Ro<63, 484, "xsnmsubqpo", []>;
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def XSMADDQP : X_VT5_VA5_VB5_FMA <63, 388, "xsmaddqp",
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[(set f128:$vT,
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(fma f128:$vA, f128:$vB,
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f128:$vTi))]>;
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def XSMADDQPO : X_VT5_VA5_VB5_FMA_Ro<63, 388, "xsmaddqpo" , []>;
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def XSMSUBQP : X_VT5_VA5_VB5_FMA <63, 420, "xsmsubqp" ,
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[(set f128:$vT,
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(fma f128:$vA, f128:$vB,
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(fneg f128:$vTi)))]>;
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def XSMSUBQPO : X_VT5_VA5_VB5_FMA_Ro<63, 420, "xsmsubqpo" , []>;
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def XSNMADDQP : X_VT5_VA5_VB5_FMA <63, 452, "xsnmaddqp",
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[(set f128:$vT,
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(fneg (fma f128:$vA, f128:$vB,
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f128:$vTi)))]>;
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def XSNMADDQPO: X_VT5_VA5_VB5_FMA_Ro<63, 452, "xsnmaddqpo", []>;
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def XSNMSUBQP : X_VT5_VA5_VB5_FMA <63, 484, "xsnmsubqp",
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[(set f128:$vT,
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(fneg (fma f128:$vA, f128:$vB,
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(fneg f128:$vTi))))]>;
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def XSNMSUBQPO: X_VT5_VA5_VB5_FMA_Ro<63, 484, "xsnmsubqpo", []>;
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// Additional fnmsub patterns: -a*c + b == -(a*c - b)
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def : Pat<(fma (fneg f128:$A), f128:$C, f128:$B), (XSNMSUBQP $B, $C, $A)>;
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def : Pat<(fma f128:$A, (fneg f128:$C), f128:$B), (XSNMSUBQP $B, $C, $A)>;
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//===--------------------------------------------------------------------===//
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// Quad/Double-Precision Compare Instructions:
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@ -0,0 +1,203 @@
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; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown \
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; RUN: -enable-ppc-quad-precision -ppc-vsr-nums-as-vr < %s | FileCheck %s
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define void @qpFmadd(fp128* nocapture readonly %a, fp128* nocapture %b,
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fp128* nocapture readonly %c, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%2 = load fp128, fp128* %c, align 16
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%madd = tail call fp128 @llvm.fmuladd.f128(fp128 %0, fp128 %1, fp128 %2)
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store fp128 %madd, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpFmadd
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; CHECK-NOT: bl fmal
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; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
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; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
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; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
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; CHECK: xsmaddqp [[REG5]], [[REG3]], [[REG4]]
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; CHECK-NEXT: stxv [[REG5]], 0(6)
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; CHECK-NEXT: blr
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}
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declare fp128 @llvm.fmuladd.f128(fp128, fp128, fp128)
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; Function Attrs: norecurse nounwind
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define void @qpFmadd_02(fp128* nocapture readonly %a,
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fp128* nocapture readonly %b,
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fp128* nocapture readonly %c, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%2 = load fp128, fp128* %c, align 16
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%mul = fmul contract fp128 %1, %2
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%add = fadd contract fp128 %0, %mul
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store fp128 %add, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpFmadd_02
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; CHECK-NOT: bl __multf3
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; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
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; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
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; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
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; CHECK: xsmaddqp [[REG3]], [[REG4]], [[REG5]]
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; CHECK-NEXT: stxv [[REG3]], 0(6)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @qpFmadd_03(fp128* nocapture readonly %a,
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fp128* nocapture readonly %b,
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fp128* nocapture readonly %c, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%mul = fmul contract fp128 %0, %1
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%2 = load fp128, fp128* %c, align 16
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%add = fadd contract fp128 %mul, %2
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store fp128 %add, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpFmadd_03
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; CHECK-NOT: bl __multf3
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; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
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; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
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; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
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; CHECK: xsmaddqp [[REG5]], [[REG3]], [[REG4]]
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; CHECK-NEXT: stxv [[REG5]], 0(6)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @qpFnmadd(fp128* nocapture readonly %a,
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fp128* nocapture readonly %b,
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fp128* nocapture readonly %c, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%2 = load fp128, fp128* %c, align 16
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%mul = fmul contract fp128 %1, %2
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%add = fadd contract fp128 %0, %mul
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%sub = fsub fp128 0xL00000000000000008000000000000000, %add
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store fp128 %sub, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpFnmadd
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; CHECK-NOT: bl __multf3
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; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
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; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
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; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
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; CHECK: xsnmaddqp [[REG3]], [[REG4]], [[REG5]]
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; CHECK-NEXT: stxv [[REG3]], 0(6)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @qpFnmadd_02(fp128* nocapture readonly %a,
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fp128* nocapture readonly %b,
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fp128* nocapture readonly %c, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%mul = fmul contract fp128 %0, %1
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%2 = load fp128, fp128* %c, align 16
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%add = fadd contract fp128 %mul, %2
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%sub = fsub fp128 0xL00000000000000008000000000000000, %add
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store fp128 %sub, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpFnmadd_02
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; CHECK-NOT: bl __multf3
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; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
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; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
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; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
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; CHECK: xsnmaddqp [[REG5]], [[REG3]], [[REG4]]
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; CHECK-NEXT: stxv [[REG5]], 0(6)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @qpFmsub(fp128* nocapture readonly %a,
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fp128* nocapture readonly %b,
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fp128* nocapture readonly %c, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%2 = load fp128, fp128* %c, align 16
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%mul = fmul contract fp128 %1, %2
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%sub = fsub contract fp128 %0, %mul
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store fp128 %sub, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpFmsub
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; CHECK-NOT: bl __multf3
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; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
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; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
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; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
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; CHECK: xsnmsubqp [[REG3]], [[REG5]], [[REG4]]
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; CHECK-NEXT: stxv [[REG3]], 0(6)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @qpFmsub_02(fp128* nocapture readonly %a,
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fp128* nocapture readonly %b,
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fp128* nocapture readonly %c, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%mul = fmul contract fp128 %0, %1
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%2 = load fp128, fp128* %c, align 16
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%sub = fsub contract fp128 %mul, %2
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store fp128 %sub, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpFmsub_02
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; CHECK-NOT: bl __multf3
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; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
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; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
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; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
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; CHECK: xsmsubqp [[REG5]], [[REG3]], [[REG4]]
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; CHECK-NEXT: stxv [[REG5]], 0(6)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @qpFnmsub(fp128* nocapture readonly %a,
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fp128* nocapture readonly %b,
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fp128* nocapture readonly %c, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%2 = load fp128, fp128* %c, align 16
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%mul = fmul contract fp128 %1, %2
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%sub = fsub contract fp128 %0, %mul
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%sub1 = fsub fp128 0xL00000000000000008000000000000000, %sub
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store fp128 %sub1, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpFnmsub
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; CHECK-NOT: bl __multf3
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; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
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; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
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; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
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; CHECK: xsnegqp [[REG4]], [[REG4]]
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; CHECK: xsnmaddqp [[REG3]], [[REG4]], [[REG5]]
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; CHECK-NEXT: stxv [[REG3]], 0(6)
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; CHECK-NEXT: blr
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}
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; Function Attrs: norecurse nounwind
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define void @qpFnmsub_02(fp128* nocapture readonly %a,
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fp128* nocapture readonly %b,
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fp128* nocapture readonly %c, fp128* nocapture %res) {
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entry:
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%0 = load fp128, fp128* %a, align 16
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%1 = load fp128, fp128* %b, align 16
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%mul = fmul contract fp128 %0, %1
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%2 = load fp128, fp128* %c, align 16
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%sub = fsub contract fp128 %mul, %2
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%sub1 = fsub fp128 0xL00000000000000008000000000000000, %sub
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store fp128 %sub1, fp128* %res, align 16
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ret void
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; CHECK-LABEL: qpFnmsub_02
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; CHECK-NOT: bl __multf3
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; CHECK-DAG: lxv [[REG3:[0-9]+]], 0(3)
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; CHECK-DAG: lxv [[REG4:[0-9]+]], 0(4)
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; CHECK-DAG: lxv [[REG5:[0-9]+]], 0(5)
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; CHECK: xsnmsubqp [[REG5]], [[REG3]], [[REG4]]
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; CHECK-NEXT: stxv [[REG5]], 0(6)
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; CHECK-NEXT: blr
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}
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